774 	x += master_priv->sarea_priv->boxes[0].x1;  in radeon_clear_box()
775 	y += master_priv->sarea_priv->boxes[0].y1;  in radeon_clear_box()
803 	if (master_priv->sarea_priv->pfCurrentPage == 1) {  in radeon_clear_box()
881 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_dispatch_clear()  local
883 	int nbox = sarea_priv->nbox;  in radeon_cp_dispatch_clear()
884 	struct drm_clip_rect *pbox = sarea_priv->boxes;  in radeon_cp_dispatch_clear()
893 	if (sarea_priv->pfCurrentPage == 1) {  in radeon_cp_dispatch_clear()
925 		sarea_priv->ctx_owner = 0;  in radeon_cp_dispatch_clear()
1002 		sarea_priv->ctx_owner = 0;  in radeon_cp_dispatch_clear()
1249 		sarea_priv->ctx_owner = 0;  in radeon_cp_dispatch_clear()
1256 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);  in radeon_cp_dispatch_clear()
1320 		sarea_priv->ctx_owner = 0;  in radeon_cp_dispatch_clear()
1327 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);  in radeon_cp_dispatch_clear()
1363 	sarea_priv->last_clear++;  in radeon_cp_dispatch_clear()
1367 	RADEON_CLEAR_AGE(sarea_priv->last_clear);  in radeon_cp_dispatch_clear()
1377 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_dispatch_swap()  local
1378 	int nbox = sarea_priv->nbox;  in radeon_cp_dispatch_swap()
1379 	struct drm_clip_rect *pbox = sarea_priv->boxes;  in radeon_cp_dispatch_swap()
1421 		if (sarea_priv->pfCurrentPage == 0) {  in radeon_cp_dispatch_swap()
1441 	sarea_priv->last_frame++;  in radeon_cp_dispatch_swap()
1445 	RADEON_FRAME_AGE(sarea_priv->last_frame);  in radeon_cp_dispatch_swap()
1456 	int offset = (master_priv->sarea_priv->pfCurrentPage == 1)  in radeon_cp_dispatch_flip()
1460 		  master_priv->sarea_priv->pfCurrentPage);  in radeon_cp_dispatch_flip()
1478 	OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base  in radeon_cp_dispatch_flip()
1487 	master_priv->sarea_priv->last_frame++;  in radeon_cp_dispatch_flip()
1488 	master_priv->sarea_priv->pfCurrentPage =  in radeon_cp_dispatch_flip()
1489 		1 - master_priv->sarea_priv->pfCurrentPage;  in radeon_cp_dispatch_flip()
1493 	RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);  in radeon_cp_dispatch_flip()
1537 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_dispatch_vertex()  local
1540 	int nbox = sarea_priv->nbox;  in radeon_cp_dispatch_vertex()
1557 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);  in radeon_cp_dispatch_vertex()
1585 	buf_priv->age = ++master_priv->sarea_priv->last_dispatch;  in radeon_cp_discard_buffer()
1643 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_dispatch_indices()  local
1650 	int nbox = sarea_priv->nbox;  in radeon_cp_dispatch_indices()
1684 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);  in radeon_cp_dispatch_indices()
2159 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_clear()  local
2168 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)  in radeon_cp_clear()
2169 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;  in radeon_cp_clear()
2172 			       sarea_priv->nbox * sizeof(depth_boxes[0])))  in radeon_cp_clear()
2203 	if (master_priv->sarea_priv->pfCurrentPage != 1)  in radeon_do_init_pageflip()
2204 		master_priv->sarea_priv->pfCurrentPage = 0;  in radeon_do_init_pageflip()
2234 	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  in radeon_cp_swap()  local
2242 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)  in radeon_cp_swap()
2243 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;  in radeon_cp_swap()
2249 	sarea_priv->ctx_owner = 0;  in radeon_cp_swap()
2259 	drm_radeon_sarea_t *sarea_priv;  in radeon_cp_vertex()  local
2267 	sarea_priv = master_priv->sarea_priv;  in radeon_cp_vertex()
2302 		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {  in radeon_cp_vertex()
2304 					      &sarea_priv->context_state,  in radeon_cp_vertex()
2305 					      sarea_priv->tex_state,  in radeon_cp_vertex()
2306 					      sarea_priv->dirty)) {  in radeon_cp_vertex()
2311 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |  in radeon_cp_vertex()
2321 		prim.vc_format = sarea_priv->vc_format;  in radeon_cp_vertex()
2338 	drm_radeon_sarea_t *sarea_priv;  in radeon_cp_indices()  local
2347 	sarea_priv = master_priv->sarea_priv;  in radeon_cp_indices()
2392 	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {  in radeon_cp_indices()
2394 				      &sarea_priv->context_state,  in radeon_cp_indices()
2395 				      sarea_priv->tex_state,  in radeon_cp_indices()
2396 				      sarea_priv->dirty)) {  in radeon_cp_indices()
2401 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |  in radeon_cp_indices()
2414 	prim.vc_format = sarea_priv->vc_format;  in radeon_cp_indices()
2545 	drm_radeon_sarea_t *sarea_priv;  in radeon_cp_vertex2()  local
2554 	sarea_priv = master_priv->sarea_priv;  in radeon_cp_vertex2()
2581 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)  in radeon_cp_vertex2()
2624 		if (sarea_priv->nbox == 1)  in radeon_cp_vertex2()
2625 			sarea_priv->nbox = 0;  in radeon_cp_vertex2()
3145 			if (master_priv->sarea_priv)  in radeon_cp_setparam()
3146 				master_priv->sarea_priv->tiling_enabled = 0;  in radeon_cp_setparam()
3151 			if (master_priv->sarea_priv)  in radeon_cp_setparam()
3152 				master_priv->sarea_priv->tiling_enabled = 1;  in radeon_cp_setparam()