Lines Matching refs:dev_priv
42 dev_priv, in radeon_check_and_fixup_offset()
47 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1; in radeon_check_and_fixup_offset()
67 if (radeon_check_offset(dev_priv, off)) in radeon_check_and_fixup_offset()
74 if (off < (dev_priv->fb_size + dev_priv->gart_size)) { in radeon_check_and_fixup_offset()
81 off = off - fb_end - 1 + dev_priv->gart_vm_start; in radeon_check_and_fixup_offset()
84 if (radeon_check_offset(dev_priv, off)) { in radeon_check_and_fixup_offset()
93 dev_priv, in radeon_check_and_fixup_packets()
104 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { in radeon_check_and_fixup_packets()
108 dev_priv->have_z_offset = 1; in radeon_check_and_fixup_packets()
115 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { in radeon_check_and_fixup_packets()
128 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { in radeon_check_and_fixup_packets()
139 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { in radeon_check_and_fixup_packets()
154 if (radeon_check_and_fixup_offset(dev_priv, in radeon_check_and_fixup_packets()
171 if (radeon_check_and_fixup_offset(dev_priv, in radeon_check_and_fixup_packets()
276 dev_priv, in radeon_check_and_fixup_packet3()
319 if (dev_priv->microcode_version != UCODE_R200) { in radeon_check_and_fixup_packet3()
342 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_check_and_fixup_packet3()
356 if (radeon_check_and_fixup_offset(dev_priv, in radeon_check_and_fixup_packet3()
377 if (dev_priv->microcode_version != UCODE_R100) { in radeon_check_and_fixup_packet3()
383 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) { in radeon_check_and_fixup_packet3()
390 if (dev_priv->microcode_version != UCODE_R200) { in radeon_check_and_fixup_packet3()
401 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) { in radeon_check_and_fixup_packet3()
417 (dev_priv, file_priv, &offset)) { in radeon_check_and_fixup_packet3()
429 (dev_priv, file_priv, &offset)) { in radeon_check_and_fixup_packet3()
449 static void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, in radeon_emit_clip_rect() argument
467 static int radeon_emit_state(drm_radeon_private_t * dev_priv, in radeon_emit_state() argument
477 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_emit_state()
483 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_emit_state()
572 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_emit_state()
592 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_emit_state()
612 if (radeon_check_and_fixup_offset(dev_priv, file_priv, in radeon_emit_state()
636 static int radeon_emit_state2(drm_radeon_private_t * dev_priv, in radeon_emit_state2() argument
650 return radeon_emit_state(dev_priv, file_priv, &state->context, in radeon_emit_state2()
767 static void radeon_clear_box(drm_radeon_private_t * dev_priv, in radeon_clear_box() argument
777 switch (dev_priv->color_fmt) { in radeon_clear_box()
799 (dev_priv->color_fmt << 8) | in radeon_clear_box()
804 OUT_RING(dev_priv->front_pitch_offset); in radeon_clear_box()
806 OUT_RING(dev_priv->back_pitch_offset); in radeon_clear_box()
817 static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_pr… in radeon_cp_performance_boxes() argument
822 if (dev_priv->stats.last_frame_reads > 1 || in radeon_cp_performance_boxes()
823 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { in radeon_cp_performance_boxes()
824 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_cp_performance_boxes()
827 if (dev_priv->stats.freelist_loops) { in radeon_cp_performance_boxes()
828 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_cp_performance_boxes()
833 if (dev_priv->stats.boxes & RADEON_BOX_FLIP) in radeon_cp_performance_boxes()
834 radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255); in radeon_cp_performance_boxes()
838 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) in radeon_cp_performance_boxes()
839 radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0); in radeon_cp_performance_boxes()
846 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) in radeon_cp_performance_boxes()
847 radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0); in radeon_cp_performance_boxes()
851 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) in radeon_cp_performance_boxes()
852 radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0); in radeon_cp_performance_boxes()
857 if (dev_priv->stats.requested_bufs) { in radeon_cp_performance_boxes()
858 if (dev_priv->stats.requested_bufs > 100) in radeon_cp_performance_boxes()
859 dev_priv->stats.requested_bufs = 100; in radeon_cp_performance_boxes()
861 radeon_clear_box(dev_priv, master_priv, 4, 16, in radeon_cp_performance_boxes()
862 dev_priv->stats.requested_bufs, 4, in radeon_cp_performance_boxes()
866 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); in radeon_cp_performance_boxes()
879 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_clear() local
882 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; in radeon_cp_dispatch_clear()
891 dev_priv->stats.clears++; in radeon_cp_dispatch_clear()
903 if (!dev_priv->have_z_offset) { in radeon_cp_dispatch_clear()
943 (dev_priv-> in radeon_cp_dispatch_clear()
949 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_clear()
965 (dev_priv-> in radeon_cp_dispatch_clear()
971 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_clear()
989 dev_priv->depth_fmt == in radeon_cp_dispatch_clear()
990 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch / in radeon_cp_dispatch_clear()
991 2) : (dev_priv-> in radeon_cp_dispatch_clear()
1004 if ((dev_priv->flags & RADEON_HAS_HIERZ) in radeon_cp_dispatch_clear()
1049 if ((dev_priv->flags & RADEON_HAS_HIERZ) in radeon_cp_dispatch_clear()
1050 && !(dev_priv->microcode_version == UCODE_R200)) { in radeon_cp_dispatch_clear()
1079 } else if (dev_priv->microcode_version == UCODE_R200) { in radeon_cp_dispatch_clear()
1133 if ((dev_priv->flags & RADEON_HAS_HIERZ) in radeon_cp_dispatch_clear()
1134 && (dev_priv->microcode_version == UCODE_R200) in radeon_cp_dispatch_clear()
1154 else if ((dev_priv->microcode_version == UCODE_R200) && in radeon_cp_dispatch_clear()
1256 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); in radeon_cp_dispatch_clear()
1327 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); in radeon_cp_dispatch_clear()
1375 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_swap() local
1386 if (dev_priv->do_boxes) in radeon_cp_dispatch_swap()
1387 radeon_cp_performance_boxes(dev_priv, master_priv); in radeon_cp_dispatch_swap()
1412 (dev_priv->color_fmt << 8) | in radeon_cp_dispatch_swap()
1422 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1423 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1425 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1426 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1453 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_flip() local
1457 ? dev_priv->front_offset : dev_priv->back_offset; in radeon_cp_dispatch_flip()
1464 if (dev_priv->do_boxes) { in radeon_cp_dispatch_flip()
1465 dev_priv->stats.boxes |= RADEON_BOX_FLIP; in radeon_cp_dispatch_flip()
1466 radeon_cp_performance_boxes(dev_priv, master_priv); in radeon_cp_dispatch_flip()
1475 ((sarea->frame.y * dev_priv->front_pitch + in radeon_cp_dispatch_flip()
1476 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) in radeon_cp_dispatch_flip()
1535 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_vertex() local
1538 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; in radeon_cp_dispatch_vertex()
1557 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); in radeon_cp_dispatch_vertex()
1580 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_discard_buffer() local
1588 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_cp_discard_buffer()
1605 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_indirect() local
1610 int offset = (dev_priv->gart_buffers_offset in radeon_cp_dispatch_indirect()
1641 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_indices() local
1644 int offset = dev_priv->gart_buffers_offset + prim->offset; in radeon_cp_dispatch_indices()
1684 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); in radeon_cp_dispatch_indices()
1701 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_texture() local
1713 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { in radeon_cp_dispatch_texture()
1718 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; in radeon_cp_dispatch_texture()
1776 if (!radeon_check_offset(dev_priv, tex->offset + image->height * in radeon_cp_dispatch_texture()
1808 radeon_do_cp_idle(dev_priv); in radeon_cp_dispatch_texture()
1898 offset = dev_priv->gart_buffers_offset + buf->offset; in radeon_cp_dispatch_texture()
1941 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_dispatch_stipple() local
1960 drm_radeon_private_t *dev_priv) in radeon_apply_surface_regs() argument
1962 if (!dev_priv->mmio) in radeon_apply_surface_regs()
1965 radeon_do_cp_idle(dev_priv); in radeon_apply_surface_regs()
1968 dev_priv->surfaces[surf_index].flags); in radeon_apply_surface_regs()
1970 dev_priv->surfaces[surf_index].lower); in radeon_apply_surface_regs()
1972 dev_priv->surfaces[surf_index].upper); in radeon_apply_surface_regs()
1987 drm_radeon_private_t *dev_priv, in alloc_surface() argument
2007 if ((dev_priv->surfaces[i].refcount != 0) && in alloc_surface()
2008 (((new_lower >= dev_priv->surfaces[i].lower) && in alloc_surface()
2009 (new_lower < dev_priv->surfaces[i].upper)) || in alloc_surface()
2010 ((new_lower < dev_priv->surfaces[i].lower) && in alloc_surface()
2011 (new_upper > dev_priv->surfaces[i].lower)))) { in alloc_surface()
2018 if (dev_priv->virt_surfaces[i].file_priv == NULL) in alloc_surface()
2028 if ((dev_priv->surfaces[i].refcount == 1) && in alloc_surface()
2029 (new->flags == dev_priv->surfaces[i].flags) && in alloc_surface()
2030 (new_upper + 1 == dev_priv->surfaces[i].lower)) { in alloc_surface()
2031 s = &(dev_priv->virt_surfaces[virt_surface_index]); in alloc_surface()
2037 dev_priv->surfaces[i].refcount++; in alloc_surface()
2038 dev_priv->surfaces[i].lower = s->lower; in alloc_surface()
2039 radeon_apply_surface_regs(s->surface_index, dev_priv); in alloc_surface()
2044 if ((dev_priv->surfaces[i].refcount == 1) && in alloc_surface()
2045 (new->flags == dev_priv->surfaces[i].flags) && in alloc_surface()
2046 (new_lower == dev_priv->surfaces[i].upper + 1)) { in alloc_surface()
2047 s = &(dev_priv->virt_surfaces[virt_surface_index]); in alloc_surface()
2053 dev_priv->surfaces[i].refcount++; in alloc_surface()
2054 dev_priv->surfaces[i].upper = s->upper; in alloc_surface()
2055 radeon_apply_surface_regs(s->surface_index, dev_priv); in alloc_surface()
2062 if (dev_priv->surfaces[i].refcount == 0) { in alloc_surface()
2063 s = &(dev_priv->virt_surfaces[virt_surface_index]); in alloc_surface()
2069 dev_priv->surfaces[i].refcount = 1; in alloc_surface()
2070 dev_priv->surfaces[i].lower = s->lower; in alloc_surface()
2071 dev_priv->surfaces[i].upper = s->upper; in alloc_surface()
2072 dev_priv->surfaces[i].flags = s->flags; in alloc_surface()
2073 radeon_apply_surface_regs(s->surface_index, dev_priv); in alloc_surface()
2083 drm_radeon_private_t * dev_priv, in free_surface() argument
2090 s = &(dev_priv->virt_surfaces[i]); in free_surface()
2094 if (dev_priv->surfaces[s->surface_index]. in free_surface()
2096 dev_priv->surfaces[s->surface_index]. in free_surface()
2099 if (dev_priv->surfaces[s->surface_index]. in free_surface()
2101 dev_priv->surfaces[s->surface_index]. in free_surface()
2104 dev_priv->surfaces[s->surface_index].refcount--; in free_surface()
2105 if (dev_priv->surfaces[s->surface_index]. in free_surface()
2107 dev_priv->surfaces[s->surface_index]. in free_surface()
2111 dev_priv); in free_surface()
2120 drm_radeon_private_t * dev_priv) in radeon_surfaces_release() argument
2124 if (dev_priv->virt_surfaces[i].file_priv == file_priv) in radeon_surfaces_release()
2125 free_surface(file_priv, dev_priv, in radeon_surfaces_release()
2126 dev_priv->virt_surfaces[i].lower); in radeon_surfaces_release()
2135 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_surface_alloc() local
2138 if (alloc_surface(alloc, dev_priv, file_priv) == -1) in radeon_surface_alloc()
2146 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_surface_free() local
2149 if (free_surface(file_priv, dev_priv, memfree->address)) in radeon_surface_free()
2157 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_clear() local
2166 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_clear()
2185 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_init_pageflip() local
2201 dev_priv->page_flipping = 1; in radeon_do_init_pageflip()
2214 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_flip() local
2219 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_flip()
2221 if (!dev_priv->page_flipping) in radeon_cp_flip()
2232 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_swap() local
2240 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_swap()
2245 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_swap()
2257 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_vertex() local
2282 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_vertex()
2283 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_vertex()
2303 if (radeon_emit_state(dev_priv, file_priv, in radeon_cp_vertex()
2336 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_indices() local
2363 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_indices()
2364 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_indices()
2393 if (radeon_emit_state(dev_priv, file_priv, in radeon_cp_indices()
2427 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_texture() local
2444 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_texture()
2445 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_texture()
2447 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_texture()
2457 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_stipple() local
2466 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_stipple()
2476 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_indirect() local
2512 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_indirect()
2513 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_indirect()
2521 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_indirect()
2543 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_vertex2() local
2565 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_vertex2()
2566 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_vertex2()
2599 if (radeon_emit_state2(dev_priv, file_priv, &state)) { in radeon_cp_vertex2()
2636 static int radeon_emit_packets(drm_radeon_private_t * dev_priv, in radeon_emit_packets() argument
2656 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, in radeon_emit_packets()
2670 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv, in radeon_emit_scalars() argument
2690 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv, in radeon_emit_scalars2() argument
2708 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, in radeon_emit_vectors() argument
2728 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, in radeon_emit_veclinear() argument
2756 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_emit_packet3() local
2763 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, in radeon_emit_packet3()
2781 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_emit_packet3_cliprect() local
2791 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, in radeon_emit_packet3_cliprect()
2821 radeon_emit_clip_rect(dev_priv, &box); in radeon_emit_packet3_cliprect()
2840 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_emit_wait() local
2870 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_cmdbuf() local
2880 RING_SPACE_TEST_WITH_RETURN(dev_priv); in radeon_cp_cmdbuf()
2881 VB_AGE_TEST_WITH_RETURN(dev_priv); in radeon_cp_cmdbuf()
2908 if (dev_priv->microcode_version == UCODE_R300) { in radeon_cp_cmdbuf()
2928 (dev_priv, file_priv, *header, cmdbuf)) { in radeon_cp_cmdbuf()
2936 if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) { in radeon_cp_cmdbuf()
2944 if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) { in radeon_cp_cmdbuf()
2989 if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) { in radeon_cp_cmdbuf()
3004 if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) { in radeon_cp_cmdbuf()
3032 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_getparam() local
3040 value = dev_priv->gart_buffers_offset; in radeon_cp_getparam()
3043 dev_priv->stats.last_frame_reads++; in radeon_cp_getparam()
3044 value = GET_SCRATCH(dev_priv, 0); in radeon_cp_getparam()
3047 value = GET_SCRATCH(dev_priv, 1); in radeon_cp_getparam()
3050 dev_priv->stats.last_clear_reads++; in radeon_cp_getparam()
3051 value = GET_SCRATCH(dev_priv, 2); in radeon_cp_getparam()
3054 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_getparam()
3060 value = dev_priv->gart_vm_start; in radeon_cp_getparam()
3063 value = dev_priv->mmio->offset; in radeon_cp_getparam()
3066 value = dev_priv->ring_rptr_offset; in radeon_cp_getparam()
3084 value = dev_priv->gart_textures_offset; in radeon_cp_getparam()
3087 if (!dev_priv->writeback_works) in radeon_cp_getparam()
3089 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_getparam()
3095 if (dev_priv->flags & RADEON_IS_PCIE) in radeon_cp_getparam()
3097 else if (dev_priv->flags & RADEON_IS_AGP) in radeon_cp_getparam()
3106 value = radeon_read_fb_location(dev_priv); in radeon_cp_getparam()
3109 value = dev_priv->num_gb_pipes; in radeon_cp_getparam()
3112 value = dev_priv->num_z_pipes; in radeon_cp_getparam()
3129 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_setparam() local
3137 radeon_priv->radeon_fb_delta = dev_priv->fb_location - in radeon_cp_setparam()
3143 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; in radeon_cp_setparam()
3144 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; in radeon_cp_setparam()
3149 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; in radeon_cp_setparam()
3150 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; in radeon_cp_setparam()
3156 dev_priv->pcigart_offset = sp->value; in radeon_cp_setparam()
3157 dev_priv->pcigart_offset_set = 1; in radeon_cp_setparam()
3160 dev_priv->new_memmap = sp->value; in radeon_cp_setparam()
3163 dev_priv->gart_info.table_size = sp->value; in radeon_cp_setparam()
3164 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) in radeon_cp_setparam()
3165 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; in radeon_cp_setparam()
3188 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_preclose() local
3189 dev_priv->page_flipping = 0; in radeon_driver_preclose()
3190 radeon_mem_release(file_priv, dev_priv->gart_heap); in radeon_driver_preclose()
3191 radeon_mem_release(file_priv, dev_priv->fb_heap); in radeon_driver_preclose()
3192 radeon_surfaces_release(file_priv, dev_priv); in radeon_driver_preclose()
3204 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_open() local
3215 if (dev_priv) in radeon_driver_open()
3216 radeon_priv->radeon_fb_delta = dev_priv->fb_location; in radeon_driver_open()