58 	for (i = 0; i < rdev->pm.num_power_states; i++) {  in radeon_pm_get_type_index()
59 		if (rdev->pm.power_state[i].type == ps_type) {  in radeon_pm_get_type_index()
66 	return rdev->pm.default_power_state_index;  in radeon_pm_get_type_index()
71 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {  in radeon_pm_acpi_event_handler()
72 		mutex_lock(&rdev->pm.mutex);  in radeon_pm_acpi_event_handler()
74 			rdev->pm.dpm.ac_power = true;  in radeon_pm_acpi_event_handler()
76 			rdev->pm.dpm.ac_power = false;  in radeon_pm_acpi_event_handler()
79 				radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);  in radeon_pm_acpi_event_handler()
81 		mutex_unlock(&rdev->pm.mutex);  in radeon_pm_acpi_event_handler()
82         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {  in radeon_pm_acpi_event_handler()
83 		if (rdev->pm.profile == PM_PROFILE_AUTO) {  in radeon_pm_acpi_event_handler()
84 			mutex_lock(&rdev->pm.mutex);  in radeon_pm_acpi_event_handler()
87 			mutex_unlock(&rdev->pm.mutex);  in radeon_pm_acpi_event_handler()
94 	switch (rdev->pm.profile) {  in radeon_pm_update_profile()
96 		rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;  in radeon_pm_update_profile()
100 			if (rdev->pm.active_crtc_count > 1)  in radeon_pm_update_profile()
101 				rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;  in radeon_pm_update_profile()
103 				rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;  in radeon_pm_update_profile()
105 			if (rdev->pm.active_crtc_count > 1)  in radeon_pm_update_profile()
106 				rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;  in radeon_pm_update_profile()
108 				rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;  in radeon_pm_update_profile()
112 		if (rdev->pm.active_crtc_count > 1)  in radeon_pm_update_profile()
113 			rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;  in radeon_pm_update_profile()
115 			rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;  in radeon_pm_update_profile()
118 		if (rdev->pm.active_crtc_count > 1)  in radeon_pm_update_profile()
119 			rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;  in radeon_pm_update_profile()
121 			rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;  in radeon_pm_update_profile()
124 		if (rdev->pm.active_crtc_count > 1)  in radeon_pm_update_profile()
125 			rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;  in radeon_pm_update_profile()
127 			rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;  in radeon_pm_update_profile()
131 	if (rdev->pm.active_crtc_count == 0) {  in radeon_pm_update_profile()
132 		rdev->pm.requested_power_state_index =  in radeon_pm_update_profile()
133 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;  in radeon_pm_update_profile()
134 		rdev->pm.requested_clock_mode_index =  in radeon_pm_update_profile()
135 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;  in radeon_pm_update_profile()
137 		rdev->pm.requested_power_state_index =  in radeon_pm_update_profile()
138 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;  in radeon_pm_update_profile()
139 		rdev->pm.requested_clock_mode_index =  in radeon_pm_update_profile()
140 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;  in radeon_pm_update_profile()
159 	if (rdev->pm.active_crtcs) {  in radeon_sync_with_vblank()
160 		rdev->pm.vblank_sync = false;  in radeon_sync_with_vblank()
162 			rdev->irq.vblank_queue, rdev->pm.vblank_sync,  in radeon_sync_with_vblank()
172 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&  in radeon_set_power_state()
173 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))  in radeon_set_power_state()
177 		sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].  in radeon_set_power_state()
178 			clock_info[rdev->pm.requested_clock_mode_index].sclk;  in radeon_set_power_state()
179 		if (sclk > rdev->pm.default_sclk)  in radeon_set_power_state()
180 			sclk = rdev->pm.default_sclk;  in radeon_set_power_state()
186 		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&  in radeon_set_power_state()
188 		    rdev->pm.active_crtc_count &&  in radeon_set_power_state()
189 		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||  in radeon_set_power_state()
190 		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))  in radeon_set_power_state()
191 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].  in radeon_set_power_state()
192 				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;  in radeon_set_power_state()
194 			mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].  in radeon_set_power_state()
195 				clock_info[rdev->pm.requested_clock_mode_index].mclk;  in radeon_set_power_state()
197 		if (mclk > rdev->pm.default_mclk)  in radeon_set_power_state()
198 			mclk = rdev->pm.default_mclk;  in radeon_set_power_state()
201 		if (sclk < rdev->pm.current_sclk)  in radeon_set_power_state()
206 		if (rdev->pm.pm_method == PM_METHOD_DYNPM) {  in radeon_set_power_state()
218 		if (sclk != rdev->pm.current_sclk) {  in radeon_set_power_state()
222 			rdev->pm.current_sclk = sclk;  in radeon_set_power_state()
227 		if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {  in radeon_set_power_state()
231 			rdev->pm.current_mclk = mclk;  in radeon_set_power_state()
241 		rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;  in radeon_set_power_state()
242 		rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;  in radeon_set_power_state()
252 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&  in radeon_pm_set_clocks()
253 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))  in radeon_pm_set_clocks()
256 	down_write(&rdev->pm.mclk_lock);  in radeon_pm_set_clocks()
269 			up_write(&rdev->pm.mclk_lock);  in radeon_pm_set_clocks()
278 			if (rdev->pm.active_crtcs & (1 << i)) {  in radeon_pm_set_clocks()
279 				rdev->pm.req_vblank |= (1 << i);  in radeon_pm_set_clocks()
289 			if (rdev->pm.req_vblank & (1 << i)) {  in radeon_pm_set_clocks()
290 				rdev->pm.req_vblank &= ~(1 << i);  in radeon_pm_set_clocks()
298 	if (rdev->pm.active_crtc_count)  in radeon_pm_set_clocks()
301 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;  in radeon_pm_set_clocks()
304 	up_write(&rdev->pm.mclk_lock);  in radeon_pm_set_clocks()
313 	DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);  in radeon_pm_print_states()
314 	for (i = 0; i < rdev->pm.num_power_states; i++) {  in radeon_pm_print_states()
315 		power_state = &rdev->pm.power_state[i];  in radeon_pm_print_states()
318 		if (i == rdev->pm.default_power_state_index)  in radeon_pm_print_states()
347 	int cp = rdev->pm.profile;  in radeon_get_pm_profile()
369 	mutex_lock(&rdev->pm.mutex);  in radeon_set_pm_profile()
370 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {  in radeon_set_pm_profile()
372 			rdev->pm.profile = PM_PROFILE_DEFAULT;  in radeon_set_pm_profile()
374 			rdev->pm.profile = PM_PROFILE_AUTO;  in radeon_set_pm_profile()
376 			rdev->pm.profile = PM_PROFILE_LOW;  in radeon_set_pm_profile()
378 			rdev->pm.profile = PM_PROFILE_MID;  in radeon_set_pm_profile()
380 			rdev->pm.profile = PM_PROFILE_HIGH;  in radeon_set_pm_profile()
391 	mutex_unlock(&rdev->pm.mutex);  in radeon_set_pm_profile()
402 	int pm = rdev->pm.pm_method;  in radeon_get_pm_method()  local
405 			(pm == PM_METHOD_DYNPM) ? "dynpm" :  in radeon_get_pm_method()
406 			(pm == PM_METHOD_PROFILE) ? "profile" : "dpm");  in radeon_get_pm_method()
425 	if (rdev->pm.pm_method == PM_METHOD_DPM) {  in radeon_set_pm_method()
431 		mutex_lock(&rdev->pm.mutex);  in radeon_set_pm_method()
432 		rdev->pm.pm_method = PM_METHOD_DYNPM;  in radeon_set_pm_method()
433 		rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;  in radeon_set_pm_method()
434 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;  in radeon_set_pm_method()
435 		mutex_unlock(&rdev->pm.mutex);  in radeon_set_pm_method()
437 		mutex_lock(&rdev->pm.mutex);  in radeon_set_pm_method()
439 		rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;  in radeon_set_pm_method()
440 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;  in radeon_set_pm_method()
441 		rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_set_pm_method()
442 		mutex_unlock(&rdev->pm.mutex);  in radeon_set_pm_method()
443 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);  in radeon_set_pm_method()
459 	enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;  in radeon_get_dpm_state()  local
462 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :  in radeon_get_dpm_state()
463 			(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");  in radeon_get_dpm_state()
474 	mutex_lock(&rdev->pm.mutex);  in radeon_set_dpm_state()
476 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;  in radeon_set_dpm_state()
478 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;  in radeon_set_dpm_state()
480 		rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;  in radeon_set_dpm_state()
482 		mutex_unlock(&rdev->pm.mutex);  in radeon_set_dpm_state()
486 	mutex_unlock(&rdev->pm.mutex);  in radeon_set_dpm_state()
503 	enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;  in radeon_get_dpm_forced_performance_level()
529 	mutex_lock(&rdev->pm.mutex);  in radeon_set_dpm_forced_performance_level()
541 		if (rdev->pm.dpm.thermal_active) {  in radeon_set_dpm_forced_performance_level()
550 	mutex_unlock(&rdev->pm.mutex);  in radeon_set_dpm_forced_performance_level()
669 	if (rdev->asic->pm.get_temperature)  in radeon_hwmon_show_temp()
686 		temp = rdev->pm.dpm.thermal.min_temp;  in radeon_hwmon_show_temp_thresh()
688 		temp = rdev->pm.dpm.thermal.max_temp;  in radeon_hwmon_show_temp_thresh()
721 	if (rdev->pm.pm_method != PM_METHOD_DPM &&  in hwmon_attributes_visible()
731 	if (rdev->pm.no_fan &&  in hwmon_attributes_visible()
775 	switch (rdev->pm.int_thermal_type) {  in radeon_hwmon_init()
784 		if (rdev->asic->pm.get_temperature == NULL)  in radeon_hwmon_init()
786 		rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,  in radeon_hwmon_init()
789 		if (IS_ERR(rdev->pm.int_hwmon_dev)) {  in radeon_hwmon_init()
790 			err = PTR_ERR(rdev->pm.int_hwmon_dev);  in radeon_hwmon_init()
804 	if (rdev->pm.int_hwmon_dev)  in radeon_hwmon_fini()
805 		hwmon_device_unregister(rdev->pm.int_hwmon_dev);  in radeon_hwmon_fini()
812 			     pm.dpm.thermal.work);  in radeon_dpm_thermal_work_handler()
816 	if (!rdev->pm.dpm_enabled)  in radeon_dpm_thermal_work_handler()
819 	if (rdev->asic->pm.get_temperature) {  in radeon_dpm_thermal_work_handler()
822 		if (temp < rdev->pm.dpm.thermal.min_temp)  in radeon_dpm_thermal_work_handler()
824 			dpm_state = rdev->pm.dpm.user_state;  in radeon_dpm_thermal_work_handler()
826 		if (rdev->pm.dpm.thermal.high_to_low)  in radeon_dpm_thermal_work_handler()
828 			dpm_state = rdev->pm.dpm.user_state;  in radeon_dpm_thermal_work_handler()
830 	mutex_lock(&rdev->pm.mutex);  in radeon_dpm_thermal_work_handler()
832 		rdev->pm.dpm.thermal_active = true;  in radeon_dpm_thermal_work_handler()
834 		rdev->pm.dpm.thermal_active = false;  in radeon_dpm_thermal_work_handler()
835 	rdev->pm.dpm.state = dpm_state;  in radeon_dpm_thermal_work_handler()
836 	mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_thermal_work_handler()
843 	bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?  in radeon_dpm_single_display()
880 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in radeon_dpm_pick_power_state()
881 		ps = &rdev->pm.dpm.ps[i];  in radeon_dpm_pick_power_state()
914 			if (rdev->pm.dpm.uvd_ps)  in radeon_dpm_pick_power_state()
915 				return rdev->pm.dpm.uvd_ps;  in radeon_dpm_pick_power_state()
935 			return rdev->pm.dpm.boot_ps;  in radeon_dpm_pick_power_state()
964 		if (rdev->pm.dpm.uvd_ps) {  in radeon_dpm_pick_power_state()
965 			return rdev->pm.dpm.uvd_ps;  in radeon_dpm_pick_power_state()
997 	if (!rdev->pm.dpm_enabled)  in radeon_dpm_change_power_state_locked()
1000 	if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {  in radeon_dpm_change_power_state_locked()
1002 		if ((!rdev->pm.dpm.thermal_active) &&  in radeon_dpm_change_power_state_locked()
1003 		    (!rdev->pm.dpm.uvd_active))  in radeon_dpm_change_power_state_locked()
1004 			rdev->pm.dpm.state = rdev->pm.dpm.user_state;  in radeon_dpm_change_power_state_locked()
1006 	dpm_state = rdev->pm.dpm.state;  in radeon_dpm_change_power_state_locked()
1010 		rdev->pm.dpm.requested_ps = ps;  in radeon_dpm_change_power_state_locked()
1015 	if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {  in radeon_dpm_change_power_state_locked()
1017 		if (ps->vce_active != rdev->pm.dpm.vce_active)  in radeon_dpm_change_power_state_locked()
1020 		if (rdev->pm.dpm.single_display != single_display)  in radeon_dpm_change_power_state_locked()
1026 			if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {  in radeon_dpm_change_power_state_locked()
1031 				rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;  in radeon_dpm_change_power_state_locked()
1032 				rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;  in radeon_dpm_change_power_state_locked()
1040 			if (rdev->pm.dpm.new_active_crtcs ==  in radeon_dpm_change_power_state_locked()
1041 			    rdev->pm.dpm.current_active_crtcs) {  in radeon_dpm_change_power_state_locked()
1044 				if ((rdev->pm.dpm.current_active_crtc_count > 1) &&  in radeon_dpm_change_power_state_locked()
1045 				    (rdev->pm.dpm.new_active_crtc_count > 1)) {  in radeon_dpm_change_power_state_locked()
1050 					rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;  in radeon_dpm_change_power_state_locked()
1051 					rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;  in radeon_dpm_change_power_state_locked()
1061 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);  in radeon_dpm_change_power_state_locked()
1063 		radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);  in radeon_dpm_change_power_state_locked()
1066 	down_write(&rdev->pm.mclk_lock);  in radeon_dpm_change_power_state_locked()
1070 	ps->vce_active = rdev->pm.dpm.vce_active;  in radeon_dpm_change_power_state_locked()
1092 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;  in radeon_dpm_change_power_state_locked()
1096 	rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;  in radeon_dpm_change_power_state_locked()
1097 	rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;  in radeon_dpm_change_power_state_locked()
1098 	rdev->pm.dpm.single_display = single_display;  in radeon_dpm_change_power_state_locked()
1101 		if (rdev->pm.dpm.thermal_active) {  in radeon_dpm_change_power_state_locked()
1102 			enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;  in radeon_dpm_change_power_state_locked()
1106 			rdev->pm.dpm.forced_level = level;  in radeon_dpm_change_power_state_locked()
1109 			radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);  in radeon_dpm_change_power_state_locked()
1115 	up_write(&rdev->pm.mclk_lock);  in radeon_dpm_change_power_state_locked()
1123 		mutex_lock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1126 		enable |= rdev->pm.dpm.sd > 0;  in radeon_dpm_enable_uvd()
1127 		enable |= rdev->pm.dpm.hd > 0;  in radeon_dpm_enable_uvd()
1130 		mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1133 			mutex_lock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1134 			rdev->pm.dpm.uvd_active = true;  in radeon_dpm_enable_uvd()
1137 			if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))  in radeon_dpm_enable_uvd()
1139 			else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))  in radeon_dpm_enable_uvd()
1141 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))  in radeon_dpm_enable_uvd()
1143 			else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))  in radeon_dpm_enable_uvd()
1148 			rdev->pm.dpm.state = dpm_state;  in radeon_dpm_enable_uvd()
1149 			mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1151 			mutex_lock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1152 			rdev->pm.dpm.uvd_active = false;  in radeon_dpm_enable_uvd()
1153 			mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_enable_uvd()
1163 		mutex_lock(&rdev->pm.mutex);  in radeon_dpm_enable_vce()
1164 		rdev->pm.dpm.vce_active = true;  in radeon_dpm_enable_vce()
1166 		rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;  in radeon_dpm_enable_vce()
1167 		mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_enable_vce()
1169 		mutex_lock(&rdev->pm.mutex);  in radeon_dpm_enable_vce()
1170 		rdev->pm.dpm.vce_active = false;  in radeon_dpm_enable_vce()
1171 		mutex_unlock(&rdev->pm.mutex);  in radeon_dpm_enable_vce()
1179 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_suspend_old()
1180 	if (rdev->pm.pm_method == PM_METHOD_DYNPM) {  in radeon_pm_suspend_old()
1181 		if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)  in radeon_pm_suspend_old()
1182 			rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;  in radeon_pm_suspend_old()
1184 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_suspend_old()
1186 	cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);  in radeon_pm_suspend_old()
1191 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_suspend_dpm()
1195 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;  in radeon_pm_suspend_dpm()
1196 	rdev->pm.dpm_enabled = false;  in radeon_pm_suspend_dpm()
1197 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_suspend_dpm()
1202 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in radeon_pm_suspend()
1214 		if (rdev->pm.default_vddc)  in radeon_pm_resume_old()
1215 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,  in radeon_pm_resume_old()
1217 		if (rdev->pm.default_vddci)  in radeon_pm_resume_old()
1218 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,  in radeon_pm_resume_old()
1220 		if (rdev->pm.default_sclk)  in radeon_pm_resume_old()
1221 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);  in radeon_pm_resume_old()
1222 		if (rdev->pm.default_mclk)  in radeon_pm_resume_old()
1223 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);  in radeon_pm_resume_old()
1226 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_resume_old()
1227 	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;  in radeon_pm_resume_old()
1228 	rdev->pm.current_clock_mode_index = 0;  in radeon_pm_resume_old()
1229 	rdev->pm.current_sclk = rdev->pm.default_sclk;  in radeon_pm_resume_old()
1230 	rdev->pm.current_mclk = rdev->pm.default_mclk;  in radeon_pm_resume_old()
1231 	if (rdev->pm.power_state) {  in radeon_pm_resume_old()
1232 …rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vol…  in radeon_pm_resume_old()
1233 …rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vo…  in radeon_pm_resume_old()
1235 	if (rdev->pm.pm_method == PM_METHOD_DYNPM  in radeon_pm_resume_old()
1236 	    && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {  in radeon_pm_resume_old()
1237 		rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;  in radeon_pm_resume_old()
1238 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,  in radeon_pm_resume_old()
1241 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_resume_old()
1250 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_resume_dpm()
1251 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;  in radeon_pm_resume_dpm()
1254 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_resume_dpm()
1257 	rdev->pm.dpm_enabled = true;  in radeon_pm_resume_dpm()
1265 		if (rdev->pm.default_vddc)  in radeon_pm_resume_dpm()
1266 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,  in radeon_pm_resume_dpm()
1268 		if (rdev->pm.default_vddci)  in radeon_pm_resume_dpm()
1269 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,  in radeon_pm_resume_dpm()
1271 		if (rdev->pm.default_sclk)  in radeon_pm_resume_dpm()
1272 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);  in radeon_pm_resume_dpm()
1273 		if (rdev->pm.default_mclk)  in radeon_pm_resume_dpm()
1274 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);  in radeon_pm_resume_dpm()
1280 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in radeon_pm_resume()
1290 	rdev->pm.profile = PM_PROFILE_DEFAULT;  in radeon_pm_init_old()
1291 	rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;  in radeon_pm_init_old()
1292 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;  in radeon_pm_init_old()
1293 	rdev->pm.dynpm_can_upclock = true;  in radeon_pm_init_old()
1294 	rdev->pm.dynpm_can_downclock = true;  in radeon_pm_init_old()
1295 	rdev->pm.default_sclk = rdev->clock.default_sclk;  in radeon_pm_init_old()
1296 	rdev->pm.default_mclk = rdev->clock.default_mclk;  in radeon_pm_init_old()
1297 	rdev->pm.current_sclk = rdev->clock.default_sclk;  in radeon_pm_init_old()
1298 	rdev->pm.current_mclk = rdev->clock.default_mclk;  in radeon_pm_init_old()
1299 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;  in radeon_pm_init_old()
1312 			if (rdev->pm.default_vddc)  in radeon_pm_init_old()
1313 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,  in radeon_pm_init_old()
1315 			if (rdev->pm.default_vddci)  in radeon_pm_init_old()
1316 				radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,  in radeon_pm_init_old()
1318 			if (rdev->pm.default_sclk)  in radeon_pm_init_old()
1319 				radeon_set_engine_clock(rdev, rdev->pm.default_sclk);  in radeon_pm_init_old()
1320 			if (rdev->pm.default_mclk)  in radeon_pm_init_old()
1321 				radeon_set_memory_clock(rdev, rdev->pm.default_mclk);  in radeon_pm_init_old()
1330 	INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);  in radeon_pm_init_old()
1332 	if (rdev->pm.num_power_states > 1) {  in radeon_pm_init_old()
1347 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in radeon_dpm_print_power_states()
1349 		radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);  in radeon_dpm_print_power_states()
1358 	rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;  in radeon_pm_init_dpm()
1359 	rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;  in radeon_pm_init_dpm()
1360 	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;  in radeon_pm_init_dpm()
1361 	rdev->pm.default_sclk = rdev->clock.default_sclk;  in radeon_pm_init_dpm()
1362 	rdev->pm.default_mclk = rdev->clock.default_mclk;  in radeon_pm_init_dpm()
1363 	rdev->pm.current_sclk = rdev->clock.default_sclk;  in radeon_pm_init_dpm()
1364 	rdev->pm.current_mclk = rdev->clock.default_mclk;  in radeon_pm_init_dpm()
1365 	rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;  in radeon_pm_init_dpm()
1377 	INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);  in radeon_pm_init_dpm()
1378 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_init_dpm()
1380 	rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;  in radeon_pm_init_dpm()
1385 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_init_dpm()
1388 	rdev->pm.dpm_enabled = true;  in radeon_pm_init_dpm()
1399 	rdev->pm.dpm_enabled = false;  in radeon_pm_init_dpm()
1403 		if (rdev->pm.default_vddc)  in radeon_pm_init_dpm()
1404 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,  in radeon_pm_init_dpm()
1406 		if (rdev->pm.default_vddci)  in radeon_pm_init_dpm()
1407 			radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,  in radeon_pm_init_dpm()
1409 		if (rdev->pm.default_sclk)  in radeon_pm_init_dpm()
1410 			radeon_set_engine_clock(rdev, rdev->pm.default_sclk);  in radeon_pm_init_dpm()
1411 		if (rdev->pm.default_mclk)  in radeon_pm_init_dpm()
1412 			radeon_set_memory_clock(rdev, rdev->pm.default_mclk);  in radeon_pm_init_dpm()
1463 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1467 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1469 			rdev->pm.pm_method = PM_METHOD_DPM;  in radeon_pm_init()
1471 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1501 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1505 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1507 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1509 			rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1511 			rdev->pm.pm_method = PM_METHOD_DPM;  in radeon_pm_init()
1515 		rdev->pm.pm_method = PM_METHOD_PROFILE;  in radeon_pm_init()
1519 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in radeon_pm_init()
1529 	if (rdev->pm.pm_method == PM_METHOD_DPM) {  in radeon_pm_late_init()
1530 		if (rdev->pm.dpm_enabled) {  in radeon_pm_late_init()
1531 			if (!rdev->pm.sysfs_initialized) {  in radeon_pm_late_init()
1545 				rdev->pm.sysfs_initialized = true;  in radeon_pm_late_init()
1548 			mutex_lock(&rdev->pm.mutex);  in radeon_pm_late_init()
1550 			mutex_unlock(&rdev->pm.mutex);  in radeon_pm_late_init()
1552 				rdev->pm.dpm_enabled = false;  in radeon_pm_late_init()
1562 		if ((rdev->pm.num_power_states > 1) &&  in radeon_pm_late_init()
1563 		    (!rdev->pm.sysfs_initialized)) {  in radeon_pm_late_init()
1572 				rdev->pm.sysfs_initialized = true;  in radeon_pm_late_init()
1580 	if (rdev->pm.num_power_states > 1) {  in radeon_pm_fini_old()
1581 		mutex_lock(&rdev->pm.mutex);  in radeon_pm_fini_old()
1582 		if (rdev->pm.pm_method == PM_METHOD_PROFILE) {  in radeon_pm_fini_old()
1583 			rdev->pm.profile = PM_PROFILE_DEFAULT;  in radeon_pm_fini_old()
1586 		} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {  in radeon_pm_fini_old()
1588 			rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;  in radeon_pm_fini_old()
1589 			rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;  in radeon_pm_fini_old()
1592 		mutex_unlock(&rdev->pm.mutex);  in radeon_pm_fini_old()
1594 		cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);  in radeon_pm_fini_old()
1601 	kfree(rdev->pm.power_state);  in radeon_pm_fini_old()
1606 	if (rdev->pm.num_power_states > 1) {  in radeon_pm_fini_dpm()
1607 		mutex_lock(&rdev->pm.mutex);  in radeon_pm_fini_dpm()
1609 		mutex_unlock(&rdev->pm.mutex);  in radeon_pm_fini_dpm()
1620 	kfree(rdev->pm.power_state);  in radeon_pm_fini_dpm()
1625 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in radeon_pm_fini()
1637 	if (rdev->pm.num_power_states < 2)  in radeon_pm_compute_clocks_old()
1640 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_compute_clocks_old()
1642 	rdev->pm.active_crtcs = 0;  in radeon_pm_compute_clocks_old()
1643 	rdev->pm.active_crtc_count = 0;  in radeon_pm_compute_clocks_old()
1649 				rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);  in radeon_pm_compute_clocks_old()
1650 				rdev->pm.active_crtc_count++;  in radeon_pm_compute_clocks_old()
1655 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {  in radeon_pm_compute_clocks_old()
1658 	} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {  in radeon_pm_compute_clocks_old()
1659 		if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {  in radeon_pm_compute_clocks_old()
1660 			if (rdev->pm.active_crtc_count > 1) {  in radeon_pm_compute_clocks_old()
1661 				if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {  in radeon_pm_compute_clocks_old()
1662 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);  in radeon_pm_compute_clocks_old()
1664 					rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;  in radeon_pm_compute_clocks_old()
1665 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;  in radeon_pm_compute_clocks_old()
1671 			} else if (rdev->pm.active_crtc_count == 1) {  in radeon_pm_compute_clocks_old()
1674 				if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {  in radeon_pm_compute_clocks_old()
1675 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;  in radeon_pm_compute_clocks_old()
1676 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;  in radeon_pm_compute_clocks_old()
1680 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,  in radeon_pm_compute_clocks_old()
1682 				} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {  in radeon_pm_compute_clocks_old()
1683 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;  in radeon_pm_compute_clocks_old()
1684 					schedule_delayed_work(&rdev->pm.dynpm_idle_work,  in radeon_pm_compute_clocks_old()
1689 				if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {  in radeon_pm_compute_clocks_old()
1690 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);  in radeon_pm_compute_clocks_old()
1692 					rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;  in radeon_pm_compute_clocks_old()
1693 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;  in radeon_pm_compute_clocks_old()
1701 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_compute_clocks_old()
1710 	if (!rdev->pm.dpm_enabled)  in radeon_pm_compute_clocks_dpm()
1713 	mutex_lock(&rdev->pm.mutex);  in radeon_pm_compute_clocks_dpm()
1716 	rdev->pm.dpm.new_active_crtcs = 0;  in radeon_pm_compute_clocks_dpm()
1717 	rdev->pm.dpm.new_active_crtc_count = 0;  in radeon_pm_compute_clocks_dpm()
1723 				rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);  in radeon_pm_compute_clocks_dpm()
1724 				rdev->pm.dpm.new_active_crtc_count++;  in radeon_pm_compute_clocks_dpm()
1731 		rdev->pm.dpm.ac_power = true;  in radeon_pm_compute_clocks_dpm()
1733 		rdev->pm.dpm.ac_power = false;  in radeon_pm_compute_clocks_dpm()
1737 	mutex_unlock(&rdev->pm.mutex);  in radeon_pm_compute_clocks_dpm()
1743 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in radeon_pm_compute_clocks()
1758 		if (rdev->pm.active_crtcs & (1 << crtc)) {  in radeon_pm_in_vbl()
1789 				pm.dynpm_idle_work.work);  in radeon_dynpm_idle_work_handler()
1792 	mutex_lock(&rdev->pm.mutex);  in radeon_dynpm_idle_work_handler()
1793 	if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {  in radeon_dynpm_idle_work_handler()
1808 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {  in radeon_dynpm_idle_work_handler()
1809 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;  in radeon_dynpm_idle_work_handler()
1810 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&  in radeon_dynpm_idle_work_handler()
1811 				   rdev->pm.dynpm_can_upclock) {  in radeon_dynpm_idle_work_handler()
1812 				rdev->pm.dynpm_planned_action =  in radeon_dynpm_idle_work_handler()
1814 				rdev->pm.dynpm_action_timeout = jiffies +  in radeon_dynpm_idle_work_handler()
1818 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {  in radeon_dynpm_idle_work_handler()
1819 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;  in radeon_dynpm_idle_work_handler()
1820 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&  in radeon_dynpm_idle_work_handler()
1821 				   rdev->pm.dynpm_can_downclock) {  in radeon_dynpm_idle_work_handler()
1822 				rdev->pm.dynpm_planned_action =  in radeon_dynpm_idle_work_handler()
1824 				rdev->pm.dynpm_action_timeout = jiffies +  in radeon_dynpm_idle_work_handler()
1832 		if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&  in radeon_dynpm_idle_work_handler()
1833 		    jiffies > rdev->pm.dynpm_action_timeout) {  in radeon_dynpm_idle_work_handler()
1838 		schedule_delayed_work(&rdev->pm.dynpm_idle_work,  in radeon_dynpm_idle_work_handler()
1841 	mutex_unlock(&rdev->pm.mutex);  in radeon_dynpm_idle_work_handler()
1860 	} else if (rdev->pm.dpm_enabled) {  in radeon_debugfs_pm_info()
1861 		mutex_lock(&rdev->pm.mutex);  in radeon_debugfs_pm_info()
1866 		mutex_unlock(&rdev->pm.mutex);  in radeon_debugfs_pm_info()
1868 		seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);  in radeon_debugfs_pm_info()
1871 			seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);  in radeon_debugfs_pm_info()
1874 		seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);  in radeon_debugfs_pm_info()
1875 		if (rdev->asic->pm.get_memory_clock)  in radeon_debugfs_pm_info()
1877 		if (rdev->pm.current_vddc)  in radeon_debugfs_pm_info()
1878 			seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);  in radeon_debugfs_pm_info()
1879 		if (rdev->asic->pm.get_pcie_lanes)  in radeon_debugfs_pm_info()