Lines Matching refs:tmp
336 u32 tmp, reg; in r100_hw_i2c_xfer() local
351 tmp = RREG32(RADEON_BIOS_6_SCRATCH); in r100_hw_i2c_xfer()
352 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); in r100_hw_i2c_xfer()
479 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
480 if (tmp & RADEON_I2C_GO) in r100_hw_i2c_xfer()
482 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
483 if (tmp & RADEON_I2C_DONE) in r100_hw_i2c_xfer()
486 DRM_DEBUG("i2c write error 0x%08x\n", tmp); in r100_hw_i2c_xfer()
487 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
511 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
512 if (tmp & RADEON_I2C_GO) in r100_hw_i2c_xfer()
514 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
515 if (tmp & RADEON_I2C_DONE) in r100_hw_i2c_xfer()
518 DRM_DEBUG("i2c read error 0x%08x\n", tmp); in r100_hw_i2c_xfer()
519 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
539 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
540 if (tmp & RADEON_I2C_GO) in r100_hw_i2c_xfer()
542 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
543 if (tmp & RADEON_I2C_DONE) in r100_hw_i2c_xfer()
546 DRM_DEBUG("i2c write error 0x%08x\n", tmp); in r100_hw_i2c_xfer()
547 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
565 tmp = RREG32(RADEON_BIOS_6_SCRATCH); in r100_hw_i2c_xfer()
566 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; in r100_hw_i2c_xfer()
567 WREG32(RADEON_BIOS_6_SCRATCH, tmp); in r100_hw_i2c_xfer()
588 u32 tmp, reg; in r500_hw_i2c_xfer() local
598 tmp = RREG32(rec->mask_clk_reg); in r500_hw_i2c_xfer()
599 tmp &= ~rec->mask_clk_mask; in r500_hw_i2c_xfer()
600 WREG32(rec->mask_clk_reg, tmp); in r500_hw_i2c_xfer()
601 tmp = RREG32(rec->mask_clk_reg); in r500_hw_i2c_xfer()
603 tmp = RREG32(rec->mask_data_reg); in r500_hw_i2c_xfer()
604 tmp &= ~rec->mask_data_mask; in r500_hw_i2c_xfer()
605 WREG32(rec->mask_data_reg, tmp); in r500_hw_i2c_xfer()
606 tmp = RREG32(rec->mask_data_reg); in r500_hw_i2c_xfer()
609 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
610 tmp &= ~rec->a_clk_mask; in r500_hw_i2c_xfer()
611 WREG32(rec->a_clk_reg, tmp); in r500_hw_i2c_xfer()
612 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
614 tmp = RREG32(rec->a_data_reg); in r500_hw_i2c_xfer()
615 tmp &= ~rec->a_data_mask; in r500_hw_i2c_xfer()
616 WREG32(rec->a_data_reg, tmp); in r500_hw_i2c_xfer()
617 tmp = RREG32(rec->a_data_reg); in r500_hw_i2c_xfer()
620 tmp = RREG32(rec->en_clk_reg); in r500_hw_i2c_xfer()
621 tmp &= ~rec->en_clk_mask; in r500_hw_i2c_xfer()
622 WREG32(rec->en_clk_reg, tmp); in r500_hw_i2c_xfer()
623 tmp = RREG32(rec->en_clk_reg); in r500_hw_i2c_xfer()
625 tmp = RREG32(rec->en_data_reg); in r500_hw_i2c_xfer()
626 tmp &= ~rec->en_data_mask; in r500_hw_i2c_xfer()
627 WREG32(rec->en_data_reg, tmp); in r500_hw_i2c_xfer()
628 tmp = RREG32(rec->en_data_reg); in r500_hw_i2c_xfer()
631 tmp = RREG32(RADEON_BIOS_6_SCRATCH); in r500_hw_i2c_xfer()
632 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); in r500_hw_i2c_xfer()
687 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
688 if (tmp & AVIVO_DC_I2C_GO) in r500_hw_i2c_xfer()
690 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
691 if (tmp & AVIVO_DC_I2C_DONE) in r500_hw_i2c_xfer()
694 DRM_DEBUG("i2c write error 0x%08x\n", tmp); in r500_hw_i2c_xfer()
729 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
730 if (tmp & AVIVO_DC_I2C_GO) in r500_hw_i2c_xfer()
732 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
733 if (tmp & AVIVO_DC_I2C_DONE) in r500_hw_i2c_xfer()
736 DRM_DEBUG("i2c read error 0x%08x\n", tmp); in r500_hw_i2c_xfer()
772 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
773 if (tmp & AVIVO_DC_I2C_GO) in r500_hw_i2c_xfer()
775 tmp = RREG32(AVIVO_DC_I2C_STATUS1); in r500_hw_i2c_xfer()
776 if (tmp & AVIVO_DC_I2C_DONE) in r500_hw_i2c_xfer()
779 DRM_DEBUG("i2c write error 0x%08x\n", tmp); in r500_hw_i2c_xfer()
802 tmp = RREG32(RADEON_BIOS_6_SCRATCH); in r500_hw_i2c_xfer()
803 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; in r500_hw_i2c_xfer()
804 WREG32(RADEON_BIOS_6_SCRATCH, tmp); in r500_hw_i2c_xfer()