117 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |  in pre_xfer()
120 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |  in pre_xfer()
131 		WREG32(rec->mask_clk_reg, temp);  in pre_xfer()
136 	WREG32(rec->a_clk_reg, temp);  in pre_xfer()
139 	WREG32(rec->a_data_reg, temp);  in pre_xfer()
143 	WREG32(rec->en_clk_reg, temp);  in pre_xfer()
146 	WREG32(rec->en_data_reg, temp);  in pre_xfer()
150 	WREG32(rec->mask_clk_reg, temp);  in pre_xfer()
154 	WREG32(rec->mask_data_reg, temp);  in pre_xfer()
169 	WREG32(rec->mask_clk_reg, temp);  in post_xfer()
173 	WREG32(rec->mask_data_reg, temp);  in post_xfer()
218 	WREG32(rec->en_clk_reg, val);  in set_clock()
231 	WREG32(rec->en_data_reg, val);  in set_data()
352 		WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);  in r100_hw_i2c_xfer()
466 		WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
470 		WREG32(i2c_data, (p->addr << 1) & 0xff);  in r100_hw_i2c_xfer()
471 		WREG32(i2c_data, 0);  in r100_hw_i2c_xfer()
472 		WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
476 		WREG32(i2c_cntl_0, reg);  in r100_hw_i2c_xfer()
487 				WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
499 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
503 				WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);  in r100_hw_i2c_xfer()
504 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
508 				WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);  in r100_hw_i2c_xfer()
519 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
526 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
530 				WREG32(i2c_data, (p->addr << 1) & 0xff);  in r100_hw_i2c_xfer()
531 				WREG32(i2c_data, p->buf[j]);  in r100_hw_i2c_xfer()
532 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
536 				WREG32(i2c_cntl_0, reg);  in r100_hw_i2c_xfer()
547 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
557 	WREG32(i2c_cntl_0, 0);  in r100_hw_i2c_xfer()
558 	WREG32(i2c_cntl_1, 0);  in r100_hw_i2c_xfer()
559 	WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
567 		WREG32(RADEON_BIOS_6_SCRATCH, tmp);  in r100_hw_i2c_xfer()
600 	WREG32(rec->mask_clk_reg, tmp);  in r500_hw_i2c_xfer()
605 	WREG32(rec->mask_data_reg, tmp);  in r500_hw_i2c_xfer()
611 	WREG32(rec->a_clk_reg, tmp);  in r500_hw_i2c_xfer()
616 	WREG32(rec->a_data_reg, tmp);  in r500_hw_i2c_xfer()
622 	WREG32(rec->en_clk_reg, tmp);  in r500_hw_i2c_xfer()
627 	WREG32(rec->en_data_reg, tmp);  in r500_hw_i2c_xfer()
632 	WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);  in r500_hw_i2c_xfer()
635 	WREG32(0x494, saved2 | 0x1);  in r500_hw_i2c_xfer()
637 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);  in r500_hw_i2c_xfer()
669 		WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
672 		WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
674 		WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
676 		WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);  in r500_hw_i2c_xfer()
677 		WREG32(AVIVO_DC_I2C_DATA, 0);  in r500_hw_i2c_xfer()
679 		WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
680 		WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
683 		WREG32(AVIVO_DC_I2C_CONTROL1, reg);  in r500_hw_i2c_xfer()
684 		WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
695 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
713 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
716 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
718 				WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
720 				WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);  in r500_hw_i2c_xfer()
721 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
722 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
725 				WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);  in r500_hw_i2c_xfer()
726 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
737 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
753 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
756 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
758 				WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
760 				WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);  in r500_hw_i2c_xfer()
762 					WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);  in r500_hw_i2c_xfer()
764 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
765 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
768 				WREG32(AVIVO_DC_I2C_CONTROL1, reg);  in r500_hw_i2c_xfer()
769 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
780 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
792 	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
795 	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
797 	WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
799 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);  in r500_hw_i2c_xfer()
800 	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);  in r500_hw_i2c_xfer()
801 	WREG32(0x494, saved2);  in r500_hw_i2c_xfer()
804 	WREG32(RADEON_BIOS_6_SCRATCH, tmp);  in r500_hw_i2c_xfer()