Lines Matching defs:drm_radeon_private
199 typedef struct drm_radeon_private { struct
200 drm_radeon_ring_buffer_t ring;
202 u32 fb_location;
203 u32 fb_size;
204 int new_memmap;
206 int gart_size;
207 u32 gart_vm_start;
208 unsigned long gart_buffers_offset;
210 int cp_mode;
211 int cp_running;
213 drm_radeon_freelist_t *head;
214 drm_radeon_freelist_t *tail;
215 int last_buf;
216 int writeback_works;
218 int usec_timeout;
220 int microcode_version;
222 struct {
231 } stats;
233 int do_boxes;
234 int page_flipping;
236 u32 color_fmt;
237 unsigned int front_offset;
238 unsigned int front_pitch;
239 unsigned int back_offset;
240 unsigned int back_pitch;
242 u32 depth_fmt;
243 unsigned int depth_offset;
244 unsigned int depth_pitch;
246 u32 front_pitch_offset;
247 u32 back_pitch_offset;
248 u32 depth_pitch_offset;
250 drm_radeon_depth_clear_t depth_clear;
252 unsigned long ring_offset;
253 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset;
255 unsigned long gart_textures_offset;
257 drm_local_map_t *sarea;
258 drm_local_map_t *cp_ring;
259 drm_local_map_t *ring_rptr;
260 drm_local_map_t *gart_textures;
262 struct mem_block *gart_heap;
263 struct mem_block *fb_heap;
266 wait_queue_head_t swi_queue;
267 atomic_t swi_emitted;
268 int vblank_crtc;
269 uint32_t irq_enable_reg;
270 uint32_t r500_disp_irq_reg;
272 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
273 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
275 unsigned long pcigart_offset;
276 unsigned int pcigart_offset_set;
277 struct drm_ati_pcigart_info gart_info;
279 u32 scratch_ages[5];
281 int have_z_offset;
284 uint32_t flags; /* see radeon_chip_flags */
285 resource_size_t fb_aper_offset;
287 int num_gb_pipes;
288 int num_z_pipes;
289 int track_flush;
290 drm_local_map_t *mmio;
293 int r600_max_pipes;
294 int r600_max_tile_pipes;
295 int r600_max_simds;
296 int r600_max_backends;
297 int r600_max_gprs;
298 int r600_max_threads;
322 } drm_radeon_private_t; argument