25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,  in radeon_dp_mst_set_be_cntl()  argument
29 	struct drm_device *dev = primary->base.dev;  in radeon_dp_mst_set_be_cntl()
35 	reg = RREG32(NI_DIG_BE_CNTL + primary->offset);  in radeon_dp_mst_set_be_cntl()
47 	DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);  in radeon_dp_mst_set_be_cntl()
48 	WREG32(NI_DIG_BE_CNTL + primary->offset, reg);  in radeon_dp_mst_set_be_cntl()
57 			DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);  in radeon_dp_mst_set_be_cntl()
62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,  in radeon_dp_mst_set_stream_attrib()  argument
67 	struct drm_device *dev = primary->base.dev;  in radeon_dp_mst_set_stream_attrib()
76 	temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);  in radeon_dp_mst_set_stream_attrib()
86 	DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);  in radeon_dp_mst_set_stream_attrib()
87 	WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);  in radeon_dp_mst_set_stream_attrib()
89 	WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);  in radeon_dp_mst_set_stream_attrib()
92 		temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);  in radeon_dp_mst_set_stream_attrib()
96 		DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);  in radeon_dp_mst_set_stream_attrib()
103 					       struct radeon_encoder *primary)  in radeon_dp_mst_update_stream_attribs()  argument
138 			radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);  in radeon_dp_mst_update_stream_attribs()
145 		radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);  in radeon_dp_mst_update_stream_attribs()
390 	struct radeon_encoder *radeon_encoder, *primary;  in radeon_mst_encoder_dpms()  local
411 	primary = mst_enc->primary;  in radeon_mst_encoder_dpms()
413 	dig_enc = primary->enc_priv;  in radeon_mst_encoder_dpms()
429 			atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);  in radeon_mst_encoder_dpms()
430 			atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,  in radeon_mst_encoder_dpms()
435 				radeon_dp_link_train(&primary->base, &mst_enc->connector->base);  in radeon_mst_encoder_dpms()
454 		radeon_dp_mst_set_be_cntl(primary, mst_enc,  in radeon_mst_encoder_dpms()
458 		radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);  in radeon_mst_encoder_dpms()
461 		atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,  in radeon_mst_encoder_dpms()
486 		radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);  in radeon_mst_encoder_dpms()
488 		radeon_dp_mst_set_be_cntl(primary, mst_enc,  in radeon_mst_encoder_dpms()
490 		atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,  in radeon_mst_encoder_dpms()
519 	mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;  in radeon_mst_mode_fixup()
521 		      mst_enc->primary->active_device, mst_enc->primary->devices,  in radeon_mst_mode_fixup()
522 		      mst_enc->connector->devices, mst_enc->primary->base.encoder_type);  in radeon_mst_mode_fixup()
542 	struct radeon_encoder *radeon_encoder, *primary;  in radeon_mst_encoder_prepare()  local
557 	primary = mst_enc->primary;  in radeon_mst_encoder_prepare()
559 	dig_enc = primary->enc_priv;  in radeon_mst_encoder_prepare()
564 		dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);  in radeon_mst_encoder_prepare()
565 		primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);  in radeon_mst_encoder_prepare()
570 	DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);  in radeon_mst_encoder_prepare()
649 	mst_enc->primary = to_radeon_encoder(enc_master);  in radeon_dp_create_fake_mst_encoder()