309 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_vblank()
315 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_vblank()
325 	    (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,  in radeon_crtc_handle_vblank()
340 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_vblank()
363 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_flip()
370 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_flip()
380 		drm_send_vblank_event(rdev->ddev, crtc_id, work->event);  in radeon_crtc_handle_flip()
382 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);  in radeon_crtc_handle_flip()
384 	drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);  in radeon_crtc_handle_flip()
463 		stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id,  in radeon_flip_work_func()
1451 			drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);  in radeon_modeset_create_props()
1459 			drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1465 		drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);  in radeon_modeset_create_props()
1469 	drm_mode_create_scaling_mode_property(rdev->ddev);  in radeon_modeset_create_props()
1473 		drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1479 		drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1484 		drm_property_create_range(rdev->ddev, 0,  in radeon_modeset_create_props()
1490 		drm_property_create_range(rdev->ddev, 0,  in radeon_modeset_create_props()
1497 		drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1503 		drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1509 		drm_property_create_enum(rdev->ddev, 0,  in radeon_modeset_create_props()
1628 	drm_mode_config_init(rdev->ddev);  in radeon_modeset_init()
1631 	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;  in radeon_modeset_init()
1634 		rdev->ddev->mode_config.max_width = 16384;  in radeon_modeset_init()
1635 		rdev->ddev->mode_config.max_height = 16384;  in radeon_modeset_init()
1637 		rdev->ddev->mode_config.max_width = 8192;  in radeon_modeset_init()
1638 		rdev->ddev->mode_config.max_height = 8192;  in radeon_modeset_init()
1640 		rdev->ddev->mode_config.max_width = 4096;  in radeon_modeset_init()
1641 		rdev->ddev->mode_config.max_height = 4096;  in radeon_modeset_init()
1644 	rdev->ddev->mode_config.preferred_depth = 24;  in radeon_modeset_init()
1645 	rdev->ddev->mode_config.prefer_shadow = 1;  in radeon_modeset_init()
1647 	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;  in radeon_modeset_init()
1665 		radeon_crtc_init(rdev->ddev, i);  in radeon_modeset_init()
1669 	ret = radeon_setup_enc_conn(rdev->ddev);  in radeon_modeset_init()
1687 	drm_kms_helper_poll_init(rdev->ddev);  in radeon_modeset_init()
1702 		drm_kms_helper_poll_fini(rdev->ddev);  in radeon_modeset_fini()
1704 		drm_mode_config_cleanup(rdev->ddev);  in radeon_modeset_fini()