Lines Matching refs:rdev
137 struct radeon_device *rdev = dev->dev_private; in radeon_is_px() local
139 if (rdev->flags & RADEON_IS_PX) in radeon_is_px()
144 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) in radeon_device_handle_px_quirks() argument
150 if (rdev->pdev->vendor == p->chip_vendor && in radeon_device_handle_px_quirks()
151 rdev->pdev->device == p->chip_device && in radeon_device_handle_px_quirks()
152 rdev->pdev->subsystem_vendor == p->subsys_vendor && in radeon_device_handle_px_quirks()
153 rdev->pdev->subsystem_device == p->subsys_device) { in radeon_device_handle_px_quirks()
154 rdev->px_quirk_flags = p->px_quirk_flags; in radeon_device_handle_px_quirks()
160 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) in radeon_device_handle_px_quirks()
161 rdev->flags &= ~RADEON_IS_PX; in radeon_device_handle_px_quirks()
174 void radeon_program_register_sequence(struct radeon_device *rdev, in radeon_program_register_sequence() argument
200 void radeon_pci_config_reset(struct radeon_device *rdev) in radeon_pci_config_reset() argument
202 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); in radeon_pci_config_reset()
212 void radeon_surface_init(struct radeon_device *rdev) in radeon_surface_init() argument
215 if (rdev->family < CHIP_R600) { in radeon_surface_init()
219 if (rdev->surface_regs[i].bo) in radeon_surface_init()
220 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); in radeon_surface_init()
222 radeon_clear_surface_reg(rdev, i); in radeon_surface_init()
239 void radeon_scratch_init(struct radeon_device *rdev) in radeon_scratch_init() argument
244 if (rdev->family < CHIP_R300) { in radeon_scratch_init()
245 rdev->scratch.num_reg = 5; in radeon_scratch_init()
247 rdev->scratch.num_reg = 7; in radeon_scratch_init()
249 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; in radeon_scratch_init()
250 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_init()
251 rdev->scratch.free[i] = true; in radeon_scratch_init()
252 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in radeon_scratch_init()
265 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) in radeon_scratch_get() argument
269 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_get()
270 if (rdev->scratch.free[i]) { in radeon_scratch_get()
271 rdev->scratch.free[i] = false; in radeon_scratch_get()
272 *reg = rdev->scratch.reg[i]; in radeon_scratch_get()
287 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) in radeon_scratch_free() argument
291 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_free()
292 if (rdev->scratch.reg[i] == reg) { in radeon_scratch_free()
293 rdev->scratch.free[i] = true; in radeon_scratch_free()
310 static int radeon_doorbell_init(struct radeon_device *rdev) in radeon_doorbell_init() argument
313 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); in radeon_doorbell_init()
314 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); in radeon_doorbell_init()
316 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); in radeon_doorbell_init()
317 if (rdev->doorbell.num_doorbells == 0) in radeon_doorbell_init()
320 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); in radeon_doorbell_init()
321 if (rdev->doorbell.ptr == NULL) { in radeon_doorbell_init()
324 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); in radeon_doorbell_init()
325 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); in radeon_doorbell_init()
327 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); in radeon_doorbell_init()
339 static void radeon_doorbell_fini(struct radeon_device *rdev) in radeon_doorbell_fini() argument
341 iounmap(rdev->doorbell.ptr); in radeon_doorbell_fini()
342 rdev->doorbell.ptr = NULL; in radeon_doorbell_fini()
354 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) in radeon_doorbell_get() argument
356 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); in radeon_doorbell_get()
357 if (offset < rdev->doorbell.num_doorbells) { in radeon_doorbell_get()
358 __set_bit(offset, rdev->doorbell.used); in radeon_doorbell_get()
374 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) in radeon_doorbell_free() argument
376 if (doorbell < rdev->doorbell.num_doorbells) in radeon_doorbell_free()
377 __clear_bit(doorbell, rdev->doorbell.used); in radeon_doorbell_free()
393 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, in radeon_doorbell_get_kfd_info() argument
400 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { in radeon_doorbell_get_kfd_info()
401 *aperture_base = rdev->doorbell.base; in radeon_doorbell_get_kfd_info()
402 *aperture_size = rdev->doorbell.size; in radeon_doorbell_get_kfd_info()
403 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); in radeon_doorbell_get_kfd_info()
425 void radeon_wb_disable(struct radeon_device *rdev) in radeon_wb_disable() argument
427 rdev->wb.enabled = false; in radeon_wb_disable()
438 void radeon_wb_fini(struct radeon_device *rdev) in radeon_wb_fini() argument
440 radeon_wb_disable(rdev); in radeon_wb_fini()
441 if (rdev->wb.wb_obj) { in radeon_wb_fini()
442 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { in radeon_wb_fini()
443 radeon_bo_kunmap(rdev->wb.wb_obj); in radeon_wb_fini()
444 radeon_bo_unpin(rdev->wb.wb_obj); in radeon_wb_fini()
445 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_fini()
447 radeon_bo_unref(&rdev->wb.wb_obj); in radeon_wb_fini()
448 rdev->wb.wb = NULL; in radeon_wb_fini()
449 rdev->wb.wb_obj = NULL; in radeon_wb_fini()
462 int radeon_wb_init(struct radeon_device *rdev) in radeon_wb_init() argument
466 if (rdev->wb.wb_obj == NULL) { in radeon_wb_init()
467 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, in radeon_wb_init()
469 &rdev->wb.wb_obj); in radeon_wb_init()
471 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); in radeon_wb_init()
474 r = radeon_bo_reserve(rdev->wb.wb_obj, false); in radeon_wb_init()
476 radeon_wb_fini(rdev); in radeon_wb_init()
479 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, in radeon_wb_init()
480 &rdev->wb.gpu_addr); in radeon_wb_init()
482 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_init()
483 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); in radeon_wb_init()
484 radeon_wb_fini(rdev); in radeon_wb_init()
487 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); in radeon_wb_init()
488 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_init()
490 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); in radeon_wb_init()
491 radeon_wb_fini(rdev); in radeon_wb_init()
497 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); in radeon_wb_init()
499 rdev->wb.use_event = false; in radeon_wb_init()
502 rdev->wb.enabled = false; in radeon_wb_init()
504 if (rdev->flags & RADEON_IS_AGP) { in radeon_wb_init()
506 rdev->wb.enabled = false; in radeon_wb_init()
507 } else if (rdev->family < CHIP_R300) { in radeon_wb_init()
509 rdev->wb.enabled = false; in radeon_wb_init()
511 rdev->wb.enabled = true; in radeon_wb_init()
513 if (rdev->family >= CHIP_R600) { in radeon_wb_init()
514 rdev->wb.use_event = true; in radeon_wb_init()
519 if (rdev->family >= CHIP_PALM) { in radeon_wb_init()
520 rdev->wb.enabled = true; in radeon_wb_init()
521 rdev->wb.use_event = true; in radeon_wb_init()
524 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); in radeon_wb_init()
570 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) in radeon_vram_location() argument
575 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { in radeon_vram_location()
576 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
581 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { in radeon_vram_location()
582 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
589 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", in radeon_vram_location()
606 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in radeon_gtt_location() argument
610 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; in radeon_gtt_location()
614 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
620 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
626 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", in radeon_gtt_location()
642 bool radeon_card_posted(struct radeon_device *rdev) in radeon_card_posted() argument
648 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && in radeon_card_posted()
649 (rdev->family < CHIP_R600)) in radeon_card_posted()
652 if (ASIC_IS_NODCE(rdev)) in radeon_card_posted()
656 if (ASIC_IS_DCE4(rdev)) { in radeon_card_posted()
659 if (rdev->num_crtc >= 4) { in radeon_card_posted()
663 if (rdev->num_crtc >= 6) { in radeon_card_posted()
669 } else if (ASIC_IS_AVIVO(rdev)) { in radeon_card_posted()
685 if (rdev->family >= CHIP_R600) in radeon_card_posted()
705 void radeon_update_bandwidth_info(struct radeon_device *rdev) in radeon_update_bandwidth_info() argument
708 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info()
709 u32 mclk = rdev->pm.current_mclk; in radeon_update_bandwidth_info()
713 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()
714 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
715 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()
716 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); in radeon_update_bandwidth_info()
718 if (rdev->flags & RADEON_IS_IGP) { in radeon_update_bandwidth_info()
721 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
734 bool radeon_boot_test_post_card(struct radeon_device *rdev) in radeon_boot_test_post_card() argument
736 if (radeon_card_posted(rdev)) in radeon_boot_test_post_card()
739 if (rdev->bios) { in radeon_boot_test_post_card()
741 if (rdev->is_atom_bios) in radeon_boot_test_post_card()
742 atom_asic_init(rdev->mode_info.atom_context); in radeon_boot_test_post_card()
744 radeon_combios_asic_init(rdev->ddev); in radeon_boot_test_post_card()
747 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in radeon_boot_test_post_card()
762 int radeon_dummy_page_init(struct radeon_device *rdev) in radeon_dummy_page_init() argument
764 if (rdev->dummy_page.page) in radeon_dummy_page_init()
766 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); in radeon_dummy_page_init()
767 if (rdev->dummy_page.page == NULL) in radeon_dummy_page_init()
769 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, in radeon_dummy_page_init()
771 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { in radeon_dummy_page_init()
772 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in radeon_dummy_page_init()
773 __free_page(rdev->dummy_page.page); in radeon_dummy_page_init()
774 rdev->dummy_page.page = NULL; in radeon_dummy_page_init()
777 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, in radeon_dummy_page_init()
789 void radeon_dummy_page_fini(struct radeon_device *rdev) in radeon_dummy_page_fini() argument
791 if (rdev->dummy_page.page == NULL) in radeon_dummy_page_fini()
793 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, in radeon_dummy_page_fini()
795 __free_page(rdev->dummy_page.page); in radeon_dummy_page_fini()
796 rdev->dummy_page.page = NULL; in radeon_dummy_page_fini()
820 struct radeon_device *rdev = info->dev->dev_private; in cail_pll_read() local
823 r = rdev->pll_rreg(rdev, reg); in cail_pll_read()
838 struct radeon_device *rdev = info->dev->dev_private; in cail_pll_write() local
840 rdev->pll_wreg(rdev, reg, val); in cail_pll_write()
854 struct radeon_device *rdev = info->dev->dev_private; in cail_mc_read() local
857 r = rdev->mc_rreg(rdev, reg); in cail_mc_read()
872 struct radeon_device *rdev = info->dev->dev_private; in cail_mc_write() local
874 rdev->mc_wreg(rdev, reg, val); in cail_mc_write()
888 struct radeon_device *rdev = info->dev->dev_private; in cail_reg_write() local
904 struct radeon_device *rdev = info->dev->dev_private; in cail_reg_read() local
922 struct radeon_device *rdev = info->dev->dev_private; in cail_ioreg_write() local
938 struct radeon_device *rdev = info->dev->dev_private; in cail_ioreg_read() local
955 int radeon_atombios_init(struct radeon_device *rdev) in radeon_atombios_init() argument
963 rdev->mode_info.atom_card_info = atom_card_info; in radeon_atombios_init()
964 atom_card_info->dev = rdev->ddev; in radeon_atombios_init()
968 if (rdev->rio_mem) { in radeon_atombios_init()
981 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); in radeon_atombios_init()
982 if (!rdev->mode_info.atom_context) { in radeon_atombios_init()
983 radeon_atombios_fini(rdev); in radeon_atombios_init()
987 mutex_init(&rdev->mode_info.atom_context->mutex); in radeon_atombios_init()
988 mutex_init(&rdev->mode_info.atom_context->scratch_mutex); in radeon_atombios_init()
989 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); in radeon_atombios_init()
990 atom_allocate_fb_scratch(rdev->mode_info.atom_context); in radeon_atombios_init()
1003 void radeon_atombios_fini(struct radeon_device *rdev) in radeon_atombios_fini() argument
1005 if (rdev->mode_info.atom_context) { in radeon_atombios_fini()
1006 kfree(rdev->mode_info.atom_context->scratch); in radeon_atombios_fini()
1008 kfree(rdev->mode_info.atom_context); in radeon_atombios_fini()
1009 rdev->mode_info.atom_context = NULL; in radeon_atombios_fini()
1010 kfree(rdev->mode_info.atom_card_info); in radeon_atombios_fini()
1011 rdev->mode_info.atom_card_info = NULL; in radeon_atombios_fini()
1030 int radeon_combios_init(struct radeon_device *rdev) in radeon_combios_init() argument
1032 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); in radeon_combios_init()
1044 void radeon_combios_fini(struct radeon_device *rdev) in radeon_combios_fini() argument
1060 struct radeon_device *rdev = cookie; in radeon_vga_set_decode() local
1061 radeon_vga_set_state(rdev, state); in radeon_vga_set_decode()
1106 static void radeon_check_arguments(struct radeon_device *rdev) in radeon_check_arguments() argument
1110 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", in radeon_check_arguments()
1116 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1120 dev_warn(rdev->dev, "gart size (%d) too small\n", in radeon_check_arguments()
1122 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1124 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", in radeon_check_arguments()
1126 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1128 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; in radeon_check_arguments()
1140 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " in radeon_check_arguments()
1147 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", in radeon_check_arguments()
1153 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", in radeon_check_arguments()
1162 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", in radeon_check_arguments()
1183 dev_warn(rdev->dev, "VM page table size (%d) too small\n", in radeon_check_arguments()
1190 dev_warn(rdev->dev, "VM page table size (%d) too large\n", in radeon_check_arguments()
1208 struct radeon_device *rdev = dev->dev_private; in radeon_switcheroo_set_state() local
1220 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) in radeon_switcheroo_set_state()
1277 int radeon_device_init(struct radeon_device *rdev, in radeon_device_init() argument
1286 rdev->shutdown = false; in radeon_device_init()
1287 rdev->dev = &pdev->dev; in radeon_device_init()
1288 rdev->ddev = ddev; in radeon_device_init()
1289 rdev->pdev = pdev; in radeon_device_init()
1290 rdev->flags = flags; in radeon_device_init()
1291 rdev->family = flags & RADEON_FAMILY_MASK; in radeon_device_init()
1292 rdev->is_atom_bios = false; in radeon_device_init()
1293 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; in radeon_device_init()
1294 rdev->mc.gtt_size = 512 * 1024 * 1024; in radeon_device_init()
1295 rdev->accel_working = false; in radeon_device_init()
1298 rdev->ring[i].idx = i; in radeon_device_init()
1300 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); in radeon_device_init()
1303 radeon_family_name[rdev->family], pdev->vendor, pdev->device, in radeon_device_init()
1308 mutex_init(&rdev->ring_lock); in radeon_device_init()
1309 mutex_init(&rdev->dc_hw_i2c_mutex); in radeon_device_init()
1310 atomic_set(&rdev->ih.lock, 0); in radeon_device_init()
1311 mutex_init(&rdev->gem.mutex); in radeon_device_init()
1312 mutex_init(&rdev->pm.mutex); in radeon_device_init()
1313 mutex_init(&rdev->gpu_clock_mutex); in radeon_device_init()
1314 mutex_init(&rdev->srbm_mutex); in radeon_device_init()
1315 mutex_init(&rdev->grbm_idx_mutex); in radeon_device_init()
1316 init_rwsem(&rdev->pm.mclk_lock); in radeon_device_init()
1317 init_rwsem(&rdev->exclusive_lock); in radeon_device_init()
1318 init_waitqueue_head(&rdev->irq.vblank_queue); in radeon_device_init()
1319 mutex_init(&rdev->mn_lock); in radeon_device_init()
1320 hash_init(rdev->mn_hash); in radeon_device_init()
1321 r = radeon_gem_init(rdev); in radeon_device_init()
1325 radeon_check_arguments(rdev); in radeon_device_init()
1329 rdev->vm_manager.max_pfn = radeon_vm_size << 18; in radeon_device_init()
1332 r = radeon_asic_init(rdev); in radeon_device_init()
1339 if ((rdev->family >= CHIP_RS400) && in radeon_device_init()
1340 (rdev->flags & RADEON_IS_IGP)) { in radeon_device_init()
1341 rdev->flags &= ~RADEON_IS_AGP; in radeon_device_init()
1344 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { in radeon_device_init()
1345 radeon_agp_disable(rdev); in radeon_device_init()
1352 if (rdev->family >= CHIP_CAYMAN) in radeon_device_init()
1353 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in radeon_device_init()
1354 else if (rdev->family >= CHIP_CEDAR) in radeon_device_init()
1355 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ in radeon_device_init()
1357 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ in radeon_device_init()
1365 rdev->need_dma32 = false; in radeon_device_init()
1366 if (rdev->flags & RADEON_IS_AGP) in radeon_device_init()
1367 rdev->need_dma32 = true; in radeon_device_init()
1368 if ((rdev->flags & RADEON_IS_PCI) && in radeon_device_init()
1369 (rdev->family <= CHIP_RS740)) in radeon_device_init()
1370 rdev->need_dma32 = true; in radeon_device_init()
1372 dma_bits = rdev->need_dma32 ? 32 : 40; in radeon_device_init()
1373 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); in radeon_device_init()
1375 rdev->need_dma32 = true; in radeon_device_init()
1379 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); in radeon_device_init()
1381 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); in radeon_device_init()
1387 spin_lock_init(&rdev->mmio_idx_lock); in radeon_device_init()
1388 spin_lock_init(&rdev->smc_idx_lock); in radeon_device_init()
1389 spin_lock_init(&rdev->pll_idx_lock); in radeon_device_init()
1390 spin_lock_init(&rdev->mc_idx_lock); in radeon_device_init()
1391 spin_lock_init(&rdev->pcie_idx_lock); in radeon_device_init()
1392 spin_lock_init(&rdev->pciep_idx_lock); in radeon_device_init()
1393 spin_lock_init(&rdev->pif_idx_lock); in radeon_device_init()
1394 spin_lock_init(&rdev->cg_idx_lock); in radeon_device_init()
1395 spin_lock_init(&rdev->uvd_idx_lock); in radeon_device_init()
1396 spin_lock_init(&rdev->rcu_idx_lock); in radeon_device_init()
1397 spin_lock_init(&rdev->didt_idx_lock); in radeon_device_init()
1398 spin_lock_init(&rdev->end_idx_lock); in radeon_device_init()
1399 if (rdev->family >= CHIP_BONAIRE) { in radeon_device_init()
1400 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); in radeon_device_init()
1401 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); in radeon_device_init()
1403 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); in radeon_device_init()
1404 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); in radeon_device_init()
1406 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); in radeon_device_init()
1407 if (rdev->rmmio == NULL) { in radeon_device_init()
1410 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); in radeon_device_init()
1411 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); in radeon_device_init()
1414 if (rdev->family >= CHIP_BONAIRE) in radeon_device_init()
1415 radeon_doorbell_init(rdev); in radeon_device_init()
1419 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { in radeon_device_init()
1420 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); in radeon_device_init()
1421 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); in radeon_device_init()
1425 if (rdev->rio_mem == NULL) in radeon_device_init()
1428 if (rdev->flags & RADEON_IS_PX) in radeon_device_init()
1429 radeon_device_handle_px_quirks(rdev); in radeon_device_init()
1434 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); in radeon_device_init()
1436 if (rdev->flags & RADEON_IS_PX) in radeon_device_init()
1438 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); in radeon_device_init()
1440 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); in radeon_device_init()
1442 r = radeon_init(rdev); in radeon_device_init()
1446 r = radeon_gem_debugfs_init(rdev); in radeon_device_init()
1451 r = radeon_mst_debugfs_init(rdev); in radeon_device_init()
1456 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { in radeon_device_init()
1460 radeon_asic_reset(rdev); in radeon_device_init()
1461 radeon_fini(rdev); in radeon_device_init()
1462 radeon_agp_disable(rdev); in radeon_device_init()
1463 r = radeon_init(rdev); in radeon_device_init()
1468 r = radeon_ib_ring_tests(rdev); in radeon_device_init()
1477 if (rdev->pm.dpm_enabled && in radeon_device_init()
1478 (rdev->pm.pm_method == PM_METHOD_DPM) && in radeon_device_init()
1479 (rdev->family == CHIP_TURKS) && in radeon_device_init()
1480 (rdev->flags & RADEON_IS_MOBILITY)) { in radeon_device_init()
1481 mutex_lock(&rdev->pm.mutex); in radeon_device_init()
1482 radeon_dpm_disable(rdev); in radeon_device_init()
1483 radeon_dpm_enable(rdev); in radeon_device_init()
1484 mutex_unlock(&rdev->pm.mutex); in radeon_device_init()
1488 if (rdev->accel_working) in radeon_device_init()
1489 radeon_test_moves(rdev); in radeon_device_init()
1494 if (rdev->accel_working) in radeon_device_init()
1495 radeon_test_syncing(rdev); in radeon_device_init()
1500 if (rdev->accel_working) in radeon_device_init()
1501 radeon_benchmark(rdev, radeon_benchmarking); in radeon_device_init()
1509 vga_switcheroo_fini_domain_pm_ops(rdev->dev); in radeon_device_init()
1513 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1523 void radeon_device_fini(struct radeon_device *rdev) in radeon_device_fini() argument
1526 rdev->shutdown = true; in radeon_device_fini()
1528 radeon_bo_evict_vram(rdev); in radeon_device_fini()
1529 radeon_fini(rdev); in radeon_device_fini()
1530 vga_switcheroo_unregister_client(rdev->pdev); in radeon_device_fini()
1531 if (rdev->flags & RADEON_IS_PX) in radeon_device_fini()
1532 vga_switcheroo_fini_domain_pm_ops(rdev->dev); in radeon_device_fini()
1533 vga_client_register(rdev->pdev, NULL, NULL, NULL); in radeon_device_fini()
1534 if (rdev->rio_mem) in radeon_device_fini()
1535 pci_iounmap(rdev->pdev, rdev->rio_mem); in radeon_device_fini()
1536 rdev->rio_mem = NULL; in radeon_device_fini()
1537 iounmap(rdev->rmmio); in radeon_device_fini()
1538 rdev->rmmio = NULL; in radeon_device_fini()
1539 if (rdev->family >= CHIP_BONAIRE) in radeon_device_fini()
1540 radeon_doorbell_fini(rdev); in radeon_device_fini()
1541 radeon_debugfs_remove_files(rdev); in radeon_device_fini()
1560 struct radeon_device *rdev; in radeon_suspend_kms() local
1569 rdev = dev->dev_private; in radeon_suspend_kms()
1603 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { in radeon_suspend_kms()
1612 radeon_bo_evict_vram(rdev); in radeon_suspend_kms()
1616 r = radeon_fence_wait_empty(rdev, i); in radeon_suspend_kms()
1619 radeon_fence_driver_force_completion(rdev, i); in radeon_suspend_kms()
1623 radeon_save_bios_scratch_regs(rdev); in radeon_suspend_kms()
1625 radeon_suspend(rdev); in radeon_suspend_kms()
1626 radeon_hpd_fini(rdev); in radeon_suspend_kms()
1628 radeon_bo_evict_vram(rdev); in radeon_suspend_kms()
1630 radeon_agp_suspend(rdev); in radeon_suspend_kms()
1641 radeon_fbdev_set_suspend(rdev, 1); in radeon_suspend_kms()
1659 struct radeon_device *rdev = dev->dev_private; in radeon_resume_kms() local
1679 radeon_agp_resume(rdev); in radeon_resume_kms()
1680 radeon_resume(rdev); in radeon_resume_kms()
1682 r = radeon_ib_ring_tests(rdev); in radeon_resume_kms()
1686 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_resume_kms()
1688 r = radeon_pm_late_init(rdev); in radeon_resume_kms()
1690 rdev->pm.dpm_enabled = false; in radeon_resume_kms()
1695 radeon_pm_resume(rdev); in radeon_resume_kms()
1698 radeon_restore_bios_scratch_regs(rdev); in radeon_resume_kms()
1711 ASIC_IS_AVIVO(rdev) ? in radeon_resume_kms()
1722 if (rdev->is_atom_bios) { in radeon_resume_kms()
1723 radeon_atom_encoder_init(rdev); in radeon_resume_kms()
1724 radeon_atom_disp_eng_pll_init(rdev); in radeon_resume_kms()
1726 if (rdev->mode_info.bl_encoder) { in radeon_resume_kms()
1727 u8 bl_level = radeon_get_backlight_level(rdev, in radeon_resume_kms()
1728 rdev->mode_info.bl_encoder); in radeon_resume_kms()
1729 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, in radeon_resume_kms()
1734 radeon_hpd_init(rdev); in radeon_resume_kms()
1749 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) in radeon_resume_kms()
1750 radeon_pm_compute_clocks(rdev); in radeon_resume_kms()
1753 radeon_fbdev_set_suspend(rdev, 0); in radeon_resume_kms()
1768 int radeon_gpu_reset(struct radeon_device *rdev) in radeon_gpu_reset() argument
1778 down_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1780 if (!rdev->needs_reset) { in radeon_gpu_reset()
1781 up_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1785 atomic_inc(&rdev->gpu_reset_counter); in radeon_gpu_reset()
1787 radeon_save_bios_scratch_regs(rdev); in radeon_gpu_reset()
1789 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); in radeon_gpu_reset()
1790 radeon_suspend(rdev); in radeon_gpu_reset()
1791 radeon_hpd_fini(rdev); in radeon_gpu_reset()
1794 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], in radeon_gpu_reset()
1798 dev_info(rdev->dev, "Saved %d dwords of commands " in radeon_gpu_reset()
1803 r = radeon_asic_reset(rdev); in radeon_gpu_reset()
1805 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); in radeon_gpu_reset()
1806 radeon_resume(rdev); in radeon_gpu_reset()
1809 radeon_restore_bios_scratch_regs(rdev); in radeon_gpu_reset()
1813 radeon_ring_restore(rdev, &rdev->ring[i], in radeon_gpu_reset()
1816 radeon_fence_driver_force_completion(rdev, i); in radeon_gpu_reset()
1821 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_gpu_reset()
1823 r = radeon_pm_late_init(rdev); in radeon_gpu_reset()
1825 rdev->pm.dpm_enabled = false; in radeon_gpu_reset()
1830 radeon_pm_resume(rdev); in radeon_gpu_reset()
1834 if (rdev->is_atom_bios) { in radeon_gpu_reset()
1835 radeon_atom_encoder_init(rdev); in radeon_gpu_reset()
1836 radeon_atom_disp_eng_pll_init(rdev); in radeon_gpu_reset()
1838 if (rdev->mode_info.bl_encoder) { in radeon_gpu_reset()
1839 u8 bl_level = radeon_get_backlight_level(rdev, in radeon_gpu_reset()
1840 rdev->mode_info.bl_encoder); in radeon_gpu_reset()
1841 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, in radeon_gpu_reset()
1846 radeon_hpd_init(rdev); in radeon_gpu_reset()
1848 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); in radeon_gpu_reset()
1850 rdev->in_reset = true; in radeon_gpu_reset()
1851 rdev->needs_reset = false; in radeon_gpu_reset()
1853 downgrade_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1855 drm_helper_resume_force_mode(rdev->ddev); in radeon_gpu_reset()
1858 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) in radeon_gpu_reset()
1859 radeon_pm_compute_clocks(rdev); in radeon_gpu_reset()
1862 r = radeon_ib_ring_tests(rdev); in radeon_gpu_reset()
1867 dev_info(rdev->dev, "GPU reset failed\n"); in radeon_gpu_reset()
1870 rdev->needs_reset = r == -EAGAIN; in radeon_gpu_reset()
1871 rdev->in_reset = false; in radeon_gpu_reset()
1873 up_read(&rdev->exclusive_lock); in radeon_gpu_reset()
1881 int radeon_debugfs_add_files(struct radeon_device *rdev, in radeon_debugfs_add_files() argument
1887 for (i = 0; i < rdev->debugfs_count; i++) { in radeon_debugfs_add_files()
1888 if (rdev->debugfs[i].files == files) { in radeon_debugfs_add_files()
1894 i = rdev->debugfs_count + 1; in radeon_debugfs_add_files()
1901 rdev->debugfs[rdev->debugfs_count].files = files; in radeon_debugfs_add_files()
1902 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; in radeon_debugfs_add_files()
1903 rdev->debugfs_count = i; in radeon_debugfs_add_files()
1906 rdev->ddev->control->debugfs_root, in radeon_debugfs_add_files()
1907 rdev->ddev->control); in radeon_debugfs_add_files()
1909 rdev->ddev->primary->debugfs_root, in radeon_debugfs_add_files()
1910 rdev->ddev->primary); in radeon_debugfs_add_files()
1915 static void radeon_debugfs_remove_files(struct radeon_device *rdev) in radeon_debugfs_remove_files() argument
1920 for (i = 0; i < rdev->debugfs_count; i++) { in radeon_debugfs_remove_files()
1921 drm_debugfs_remove_files(rdev->debugfs[i].files, in radeon_debugfs_remove_files()
1922 rdev->debugfs[i].num_files, in radeon_debugfs_remove_files()
1923 rdev->ddev->control); in radeon_debugfs_remove_files()
1924 drm_debugfs_remove_files(rdev->debugfs[i].files, in radeon_debugfs_remove_files()
1925 rdev->debugfs[i].num_files, in radeon_debugfs_remove_files()
1926 rdev->ddev->primary); in radeon_debugfs_remove_files()