Lines Matching refs:tmp
195 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
198 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
200 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
388 uint32_t tmp; in radeon_legacy_set_engine_clock() local
395 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
396 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
397 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
399 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
400 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
401 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
405 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
406 tmp |= RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
407 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
411 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
412 tmp |= RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
413 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
417 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_set_engine_clock()
418 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); in radeon_legacy_set_engine_clock()
419 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; in radeon_legacy_set_engine_clock()
420 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
423 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
424 tmp &= ~RADEON_SPLL_PVG_MASK; in radeon_legacy_set_engine_clock()
426 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
428 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
429 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
431 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
432 tmp &= ~RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
433 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
437 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
438 tmp &= ~RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
439 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
443 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
444 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
448 tmp |= 1; in radeon_legacy_set_engine_clock()
451 tmp |= 2; in radeon_legacy_set_engine_clock()
454 tmp |= 3; in radeon_legacy_set_engine_clock()
457 tmp |= 4; in radeon_legacy_set_engine_clock()
460 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
464 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
465 tmp |= RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
466 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
473 uint32_t tmp; in radeon_legacy_set_clock_gating() local
477 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
481 tmp &= in radeon_legacy_set_clock_gating()
485 tmp &= in radeon_legacy_set_clock_gating()
491 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
495 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
496 tmp &= in radeon_legacy_set_clock_gating()
510 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
511 tmp |= in radeon_legacy_set_clock_gating()
514 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
516 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
517 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
518 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
519 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
521 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
522 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
524 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
526 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
527 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
540 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
542 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
543 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
546 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | in radeon_legacy_set_clock_gating()
549 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
551 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
552 tmp &= in radeon_legacy_set_clock_gating()
566 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
567 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
569 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
570 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
571 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
572 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
574 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
575 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
577 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
579 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
580 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
593 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
595 tmp = RREG32_PLL(RADEON_MCLK_MISC); in radeon_legacy_set_clock_gating()
596 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | in radeon_legacy_set_clock_gating()
598 WREG32_PLL(RADEON_MCLK_MISC, tmp); in radeon_legacy_set_clock_gating()
600 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
601 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
604 tmp &= ~(RADEON_FORCEON_YCLKA | in radeon_legacy_set_clock_gating()
612 if ((tmp & R300_DISABLE_MC_MCLKA) && in radeon_legacy_set_clock_gating()
613 (tmp & R300_DISABLE_MC_MCLKB)) { in radeon_legacy_set_clock_gating()
615 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
619 tmp &= in radeon_legacy_set_clock_gating()
622 tmp &= in radeon_legacy_set_clock_gating()
625 tmp &= ~(R300_DISABLE_MC_MCLKA | in radeon_legacy_set_clock_gating()
630 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
632 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
633 tmp &= ~(R300_SCLK_FORCE_VAP); in radeon_legacy_set_clock_gating()
634 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
635 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
638 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
639 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
642 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
645 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
647 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | in radeon_legacy_set_clock_gating()
651 tmp |= (RADEON_ENGIN_DYNCLK_MODE | in radeon_legacy_set_clock_gating()
653 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
656 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_clock_gating()
657 tmp |= RADEON_SCLK_DYN_START_CNTL; in radeon_legacy_set_clock_gating()
658 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_clock_gating()
664 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
666 tmp &= ~RADEON_SCLK_FORCEON_MASK; in radeon_legacy_set_clock_gating()
678 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
679 tmp |= RADEON_SCLK_FORCE_VIP; in radeon_legacy_set_clock_gating()
682 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
687 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
688 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
696 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
698 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
708 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
709 tmp |= RADEON_TCL_BYPASS_DISABLE; in radeon_legacy_set_clock_gating()
710 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
715 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
716 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
724 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
727 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
728 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
731 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
737 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
738 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
745 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
748 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
749 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
757 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
759 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
760 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
761 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
763 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
764 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
767 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
769 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
770 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
784 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
787 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
788 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
790 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
792 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
793 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
801 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
803 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
804 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
805 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
807 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
808 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
812 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
814 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
815 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
818 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
820 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
821 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
835 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
837 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
838 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); in radeon_legacy_set_clock_gating()
839 tmp |= RADEON_SCLK_FORCE_SE; in radeon_legacy_set_clock_gating()
842 tmp |= (RADEON_SCLK_FORCE_RB | in radeon_legacy_set_clock_gating()
855 tmp |= (RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
862 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
868 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
869 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
872 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
877 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
878 tmp &= ~(RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
880 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
887 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
888 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
889 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
893 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
894 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
902 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
905 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
906 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
908 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()