1023 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1085 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1087 		track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;  in r600_cs_check_reg()
1106 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1215 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1246 			ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1282 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1285 		track->cb_color_bo_mc[tmp] = reloc->gpu_offset;  in r600_cs_check_reg()
1296 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1298 		track->db_bo_mc = reloc->gpu_offset;  in r600_cs_check_reg()
1309 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1378 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1387 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_cs_check_reg()
1673 		offset = reloc->gpu_offset +  in r600_packet3_check()
1714 		offset = reloc->gpu_offset +  in r600_packet3_check()
1766 			offset = reloc->gpu_offset +  in r600_packet3_check()
1806 			offset = reloc->gpu_offset + tmp;  in r600_packet3_check()
1836 			offset = reloc->gpu_offset + tmp;  in r600_packet3_check()
1862 			ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
1878 			offset = reloc->gpu_offset +  in r600_packet3_check()
1900 		offset = reloc->gpu_offset +  in r600_packet3_check()
1965 				base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
1979 				mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
2009 				offset64 = reloc->gpu_offset + offset;  in r600_packet3_check()
2119 			ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);  in r600_packet3_check()
2152 			offset += reloc->gpu_offset;  in r600_packet3_check()
2171 			offset += reloc->gpu_offset;  in r600_packet3_check()
2200 		offset += reloc->gpu_offset;  in r600_packet3_check()
2225 			offset += reloc->gpu_offset;  in r600_packet3_check()
2249 			offset += reloc->gpu_offset;  in r600_packet3_check()
2506 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2512 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2513 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2540 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2544 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2545 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2550 					ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2551 					ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2555 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2565 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2566 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2567 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2568 					ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2576 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2577 					ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2578 					ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2579 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2611 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2612 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()