2476 	struct radeon_bo_list *src_reloc, *dst_reloc;  in r600_dma_cs_parse()  local
2497 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2506 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2512 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2513 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2516 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2518 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2528 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2544 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2545 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2555 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2565 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2567 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2576 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2579 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2588 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2590 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2599 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2606 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2608 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2611 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2612 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()