Lines Matching refs:base_offset
354 u64 base_offset, base_align; in r600_cs_track_validate_cb() local
379 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; in r600_cs_track_validate_cb()
422 if (!IS_ALIGNED(base_offset, base_align)) { in r600_cs_track_validate_cb()
424 base_offset, base_align, array_mode); in r600_cs_track_validate_cb()
523 u64 base_offset, base_align; in r600_cs_track_validate_db() local
574 base_offset = track->db_bo_mc + track->db_offset; in r600_cs_track_validate_db()
613 if (!IS_ALIGNED(base_offset, base_align)) { in r600_cs_track_validate_db()
615 base_offset, base_align, array_mode); in r600_cs_track_validate_db()
1472 u64 base_offset, in r600_check_texture_resource() argument
1491 base_offset <<= 8; in r600_check_texture_resource()
1569 if (!IS_ALIGNED(base_offset, base_align)) { in r600_check_texture_resource()
1571 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); in r600_check_texture_resource()
1955 u32 size, offset, base_offset, mip_offset; in r600_packet3_check() local
1965 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), in r600_packet3_check()
1988 ib[idx+1+(i*7)+2] += base_offset; in r600_packet3_check()