Lines Matching refs:dev_priv

77 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)  in set_render_target()  argument
92 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && in set_render_target()
93 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { in set_render_target()
135 cp_set_surface_sync(drm_radeon_private_t *dev_priv, in cp_set_surface_sync() argument
159 drm_radeon_private_t *dev_priv = dev->dev_private; in set_shaders() local
168 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); in set_shaders()
169 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); in set_shaders()
176 dev_priv->blit_vb->used = 512; in set_shaders()
178 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
215 cp_set_surface_sync(dev_priv, in set_shaders()
220 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) in set_vtx_resource() argument
243 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in set_vtx_resource()
244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in set_vtx_resource()
245 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in set_vtx_resource()
246 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || in set_vtx_resource()
247 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) in set_vtx_resource()
248 cp_set_surface_sync(dev_priv, in set_vtx_resource()
251 cp_set_surface_sync(dev_priv, in set_vtx_resource()
256 set_tex_resource(drm_radeon_private_t *dev_priv, in set_tex_resource() argument
294 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) in set_scissors() argument
318 draw_auto(drm_radeon_private_t *dev_priv) in draw_auto() argument
347 set_default_state(drm_radeon_private_t *dev_priv) in set_default_state() argument
357 switch ((dev_priv->flags & RADEON_FAMILY_MASK)) { in set_default_state()
471 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in set_default_state()
472 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in set_default_state()
473 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in set_default_state()
474 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || in set_default_state()
475 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) in set_default_state()
501 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { in set_default_state()
526 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_nomm_get_vb() local
527 dev_priv->blit_vb = radeon_freelist_get(dev); in r600_nomm_get_vb()
528 if (!dev_priv->blit_vb) { in r600_nomm_get_vb()
537 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_nomm_put_vb() local
539 dev_priv->blit_vb->used = 0; in r600_nomm_put_vb()
540 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); in r600_nomm_put_vb()
545 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_nomm_get_vb_ptr() local
547 dev_priv->blit_vb->offset + dev_priv->blit_vb->used)); in r600_nomm_get_vb_ptr()
553 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_prepare_blit_copy() local
561 dev_priv->blit_vb->file_priv = file_priv; in r600_prepare_blit_copy()
563 set_default_state(dev_priv); in r600_prepare_blit_copy()
573 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_done_blit_copy() local
596 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_blit_copy() local
631 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { in r600_blit_copy()
635 if (!dev_priv->blit_vb) in r600_blit_copy()
657 set_tex_resource(dev_priv, FMT_8, in r600_blit_copy()
661 cp_set_surface_sync(dev_priv, in r600_blit_copy()
665 set_render_target(dev_priv, COLOR_8, in r600_blit_copy()
670 set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h); in r600_blit_copy()
673 vb_addr = dev_priv->gart_buffers_offset + in r600_blit_copy()
674 dev_priv->blit_vb->offset + in r600_blit_copy()
675 dev_priv->blit_vb->used; in r600_blit_copy()
676 set_vtx_resource(dev_priv, vb_addr); in r600_blit_copy()
679 draw_auto(dev_priv); in r600_blit_copy()
681 cp_set_surface_sync(dev_priv, in r600_blit_copy()
686 dev_priv->blit_vb->used += 12 * 4; in r600_blit_copy()
720 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { in r600_blit_copy()
723 if (!dev_priv->blit_vb) in r600_blit_copy()
746 set_tex_resource(dev_priv, FMT_8_8_8_8, in r600_blit_copy()
751 cp_set_surface_sync(dev_priv, in r600_blit_copy()
755 set_render_target(dev_priv, COLOR_8_8_8_8, in r600_blit_copy()
760 set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h); in r600_blit_copy()
763 vb_addr = dev_priv->gart_buffers_offset + in r600_blit_copy()
764 dev_priv->blit_vb->offset + in r600_blit_copy()
765 dev_priv->blit_vb->used; in r600_blit_copy()
766 set_vtx_resource(dev_priv, vb_addr); in r600_blit_copy()
769 draw_auto(dev_priv); in r600_blit_copy()
771 cp_set_surface_sync(dev_priv, in r600_blit_copy()
776 dev_priv->blit_vb->used += 12 * 4; in r600_blit_copy()
791 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_blit_swap() local
797 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { in r600_blit_swap()
801 if (!dev_priv->blit_vb) in r600_blit_swap()
844 set_tex_resource(dev_priv, tex_format, in r600_blit_swap()
849 cp_set_surface_sync(dev_priv, in r600_blit_swap()
853 set_render_target(dev_priv, cb_format, in r600_blit_swap()
858 set_scissors(dev_priv, dx, dy, dx2, dy2); in r600_blit_swap()
861 vb_addr = dev_priv->gart_buffers_offset + in r600_blit_swap()
862 dev_priv->blit_vb->offset + in r600_blit_swap()
863 dev_priv->blit_vb->used; in r600_blit_swap()
864 set_vtx_resource(dev_priv, vb_addr); in r600_blit_swap()
867 draw_auto(dev_priv); in r600_blit_swap()
869 cp_set_surface_sync(dev_priv, in r600_blit_swap()
873 dev_priv->blit_vb->used += 12 * 4; in r600_blit_swap()