Lines Matching refs:tmp
298 u32 tmp = 0; in dce3_program_fmt() local
323 tmp |= FMT_SPATIAL_DITHER_EN; in dce3_program_fmt()
325 tmp |= FMT_TRUNCATE_EN; in dce3_program_fmt()
330 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); in dce3_program_fmt()
332 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); in dce3_program_fmt()
340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
856 u32 tmp; in r600_hpd_set_polarity() local
862 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
864 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
866 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
867 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
870 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_hpd_set_polarity()
872 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
874 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
875 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
878 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_hpd_set_polarity()
880 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
882 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
883 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
886 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_hpd_set_polarity()
888 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
890 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
891 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_hpd_set_polarity()
894 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
896 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
898 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
899 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
903 tmp = RREG32(DC_HPD6_INT_CONTROL); in r600_hpd_set_polarity()
905 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
907 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
908 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_hpd_set_polarity()
916 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_hpd_set_polarity()
918 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
920 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
921 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
924 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_hpd_set_polarity()
926 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
928 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
929 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
932 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_hpd_set_polarity()
934 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
936 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
937 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
963 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); in r600_hpd_init() local
965 tmp |= DC_HPDx_EN; in r600_hpd_init()
969 WREG32(DC_HPD1_CONTROL, tmp); in r600_hpd_init()
972 WREG32(DC_HPD2_CONTROL, tmp); in r600_hpd_init()
975 WREG32(DC_HPD3_CONTROL, tmp); in r600_hpd_init()
978 WREG32(DC_HPD4_CONTROL, tmp); in r600_hpd_init()
982 WREG32(DC_HPD5_CONTROL, tmp); in r600_hpd_init()
985 WREG32(DC_HPD6_CONTROL, tmp); in r600_hpd_init()
1069 u32 tmp; in r600_pcie_gart_tlb_flush() local
1075 u32 tmp; in r600_pcie_gart_tlb_flush() local
1083 tmp = readl((void __iomem *)ptr); in r600_pcie_gart_tlb_flush()
1092 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in r600_pcie_gart_tlb_flush()
1093 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; in r600_pcie_gart_tlb_flush()
1094 if (tmp == 2) { in r600_pcie_gart_tlb_flush()
1098 if (tmp) { in r600_pcie_gart_tlb_flush()
1123 u32 tmp; in r600_pcie_gart_enable() local
1141 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1145 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1146 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1147 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_pcie_gart_enable()
1148 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_enable()
1149 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_enable()
1150 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_enable()
1151 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_enable()
1152 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_enable()
1153 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1154 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1155 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1156 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1157 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1158 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1159 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1160 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1181 u32 tmp; in r600_pcie_gart_disable() local
1193 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | in r600_pcie_gart_disable()
1195 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_disable()
1196 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_disable()
1197 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_disable()
1198 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_disable()
1199 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1200 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1201 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1202 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1203 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1204 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1205 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1206 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1207 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1208 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1209 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1210 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1223 u32 tmp; in r600_agp_enable() local
1233 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
1237 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_agp_enable()
1238 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_agp_enable()
1239 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_agp_enable()
1240 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_agp_enable()
1241 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_agp_enable()
1242 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_agp_enable()
1243 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_agp_enable()
1244 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_agp_enable()
1245 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_agp_enable()
1246 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_agp_enable()
1247 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_agp_enable()
1248 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_agp_enable()
1249 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1250 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1258 u32 tmp; in r600_mc_wait_for_idle() local
1262 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; in r600_mc_wait_for_idle()
1263 if (!tmp) in r600_mc_wait_for_idle()
1298 u32 tmp; in r600_mc_program() local
1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1339 WREG32(MC_VM_FB_LOCATION, tmp); in r600_mc_program()
1428 u32 tmp; in r600_mc_init() local
1435 tmp = RREG32(RAMCFG); in r600_mc_init()
1436 if (tmp & CHANSIZE_OVERRIDE) { in r600_mc_init()
1438 } else if (tmp & CHANSIZE_MASK) { in r600_mc_init()
1443 tmp = RREG32(CHMAP); in r600_mc_init()
1444 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in r600_mc_init()
1549 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); in r600_set_bios_scratch_engine_hung() local
1552 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; in r600_set_bios_scratch_engine_hung()
1554 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; in r600_set_bios_scratch_engine_hung()
1556 WREG32(R600_BIOS_3_SCRATCH, tmp); in r600_set_bios_scratch_engine_hung()
1583 u32 i, j, tmp; in r600_is_display_hung() local
1595 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1596 if (tmp != crtc_status[i]) in r600_is_display_hung()
1611 u32 tmp; in r600_gpu_check_soft_reset() local
1614 tmp = RREG32(R_008010_GRBM_STATUS); in r600_gpu_check_soft_reset()
1616 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | in r600_gpu_check_soft_reset()
1617 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1618 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | in r600_gpu_check_soft_reset()
1619 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | in r600_gpu_check_soft_reset()
1620 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) in r600_gpu_check_soft_reset()
1623 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | in r600_gpu_check_soft_reset()
1624 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1625 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | in r600_gpu_check_soft_reset()
1626 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | in r600_gpu_check_soft_reset()
1627 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) in r600_gpu_check_soft_reset()
1631 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | in r600_gpu_check_soft_reset()
1632 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) in r600_gpu_check_soft_reset()
1635 if (G_008010_GRBM_EE_BUSY(tmp)) in r600_gpu_check_soft_reset()
1639 tmp = RREG32(DMA_STATUS_REG); in r600_gpu_check_soft_reset()
1640 if (!(tmp & DMA_IDLE)) in r600_gpu_check_soft_reset()
1644 tmp = RREG32(R_000E50_SRBM_STATUS); in r600_gpu_check_soft_reset()
1645 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) in r600_gpu_check_soft_reset()
1648 if (G_000E50_IH_BUSY(tmp)) in r600_gpu_check_soft_reset()
1651 if (G_000E50_SEM_BUSY(tmp)) in r600_gpu_check_soft_reset()
1654 if (G_000E50_GRBM_RQ_PENDING(tmp)) in r600_gpu_check_soft_reset()
1657 if (G_000E50_VMC_BUSY(tmp)) in r600_gpu_check_soft_reset()
1660 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | in r600_gpu_check_soft_reset()
1661 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1662 G_000E50_MCDW_BUSY(tmp)) in r600_gpu_check_soft_reset()
1681 u32 tmp; in r600_gpu_soft_reset() local
1701 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1702 tmp &= ~DMA_RB_ENABLE; in r600_gpu_soft_reset()
1703 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1777 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1778 tmp |= grbm_soft_reset; in r600_gpu_soft_reset()
1779 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1780 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1781 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1785 tmp &= ~grbm_soft_reset; in r600_gpu_soft_reset()
1786 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1787 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1791 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1792 tmp |= srbm_soft_reset; in r600_gpu_soft_reset()
1793 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1794 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1795 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1799 tmp &= ~srbm_soft_reset; in r600_gpu_soft_reset()
1800 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1801 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1816 u32 tmp, i; in r600_gpu_pci_config_reset() local
1832 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1833 tmp &= ~DMA_RB_ENABLE; in r600_gpu_pci_config_reset()
1834 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
1850 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
1851 tmp |= VGA_COHE_SPEC_TIMER_DIS; in r600_gpu_pci_config_reset()
1852 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()
1854 tmp = RREG32(BIF_SCRATCH0); in r600_gpu_pci_config_reset()
1861 tmp = SOFT_RESET_BIF; in r600_gpu_pci_config_reset()
1862 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_pci_config_reset()
1929 u32 pipe_rb_ratio, pipe_rb_remain, tmp; in r6xx_remap_render_backend() local
1934 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); in r6xx_remap_render_backend()
1936 if ((tmp & 0xff) != 0xff) in r6xx_remap_render_backend()
1937 disabled_rb_mask = tmp; in r6xx_remap_render_backend()
1982 u32 tmp; in r600_gpu_init() local
2097 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; in r600_gpu_init()
2098 if (tmp > 3) { in r600_gpu_init()
2102 tiling_config |= ROW_TILING(tmp); in r600_gpu_init()
2103 tiling_config |= SAMPLE_SPLIT(tmp); in r600_gpu_init()
2108 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2110 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2113 tmp = 0; in r600_gpu_init()
2115 tmp |= (1 << i); in r600_gpu_init()
2117 if ((disabled_rb_mask & tmp) == tmp) { in r600_gpu_init()
2121 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; in r600_gpu_init()
2122 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2124 tiling_config |= tmp << 16; in r600_gpu_init()
2125 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2133 …tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >>… in r600_gpu_init()
2134 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); in r600_gpu_init()
2135 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
2147 tmp = RREG32(SX_DEBUG_1); in r600_gpu_init()
2148 tmp |= SMX_EVENT_RELEASE; in r600_gpu_init()
2150 tmp |= ENABLE_NEW_SMX_ADDRESS; in r600_gpu_init()
2151 WREG32(SX_DEBUG_1, tmp); in r600_gpu_init()
2172 tmp = RREG32(SQ_MS_FIFO_SIZES); in r600_gpu_init()
2177 tmp = (CACHE_FIFO_SIZE(0xa) | in r600_gpu_init()
2183 tmp &= ~DONE_FIFO_HIWATER(0xff); in r600_gpu_init()
2184 tmp |= DONE_FIFO_HIWATER(0x4); in r600_gpu_init()
2186 WREG32(SQ_MS_FIFO_SIZES, tmp); in r600_gpu_init()
2301 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2307 tmp += 32; in r600_gpu_init()
2310 tmp += 128; in r600_gpu_init()
2315 if (tmp > 256) { in r600_gpu_init()
2316 tmp = 256; in r600_gpu_init()
2319 WREG32(VGT_GS_PER_ES, tmp); in r600_gpu_init()
2350 tmp = TC_L2_SIZE(8); in r600_gpu_init()
2354 tmp = TC_L2_SIZE(4); in r600_gpu_init()
2357 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; in r600_gpu_init()
2360 tmp = TC_L2_SIZE(0); in r600_gpu_init()
2363 WREG32(TC_CNTL, tmp); in r600_gpu_init()
2365 tmp = RREG32(HDP_HOST_PATH_CNTL); in r600_gpu_init()
2366 WREG32(HDP_HOST_PATH_CNTL, tmp); in r600_gpu_init()
2368 tmp = RREG32(ARB_POP); in r600_gpu_init()
2369 tmp |= ENABLE_TC128; in r600_gpu_init()
2370 WREG32(ARB_POP, tmp); in r600_gpu_init()
2716 u32 tmp; in r600_cp_resume() local
2728 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2730 tmp |= BUF_SWAP_32BIT; in r600_cp_resume()
2732 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2739 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in r600_cp_resume()
2753 tmp |= RB_NO_UPDATE; in r600_cp_resume()
2758 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2823 uint32_t tmp = 0; in r600_ring_test() local
2844 tmp = RREG32(scratch); in r600_ring_test()
2845 if (tmp == 0xDEADBEEF) in r600_ring_test()
2853 ring->idx, scratch, tmp); in r600_ring_test()
2970 u32 size_in_bytes, cur_size_in_bytes, tmp; in r600_copy_cpdma() local
2996 tmp = upper_32_bits(src_offset) & 0xff; in r600_copy_cpdma()
2998 tmp |= PACKET3_CP_DMA_CP_SYNC; in r600_copy_cpdma()
3001 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
3360 uint32_t tmp = 0; in r600_ib_test() local
3390 tmp = RREG32(scratch); in r600_ib_test()
3391 if (tmp == 0xDEADBEEF) in r600_ib_test()
3399 scratch, tmp); in r600_ib_test()
3574 u32 tmp; in r600_disable_interrupt_state() local
3577 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3578 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3586 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3587 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3588 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3589 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3590 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3591 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3592 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3593 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3595 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3596 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3597 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3598 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3599 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3600 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_disable_interrupt_state()
3601 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3602 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_disable_interrupt_state()
3604 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3605 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3606 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3607 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3612 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3613 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3614 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3615 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3616 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3617 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3618 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3619 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3620 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3621 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3868 u32 tmp; in r600_irq_ack() local
3905 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3906 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3907 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
3909 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_irq_ack()
3910 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3911 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_irq_ack()
3916 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_irq_ack()
3917 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3918 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_irq_ack()
3920 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_irq_ack()
3921 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3922 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_irq_ack()
3927 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_irq_ack()
3928 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3929 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_irq_ack()
3931 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_irq_ack()
3932 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3933 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_irq_ack()
3937 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_irq_ack()
3938 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3939 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_irq_ack()
3943 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3944 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3945 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
3948 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3949 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3950 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_irq_ack()
3953 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3954 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3955 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_irq_ack()
3958 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3959 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3960 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_irq_ack()
3964 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3965 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3966 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3970 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3971 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3972 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3974 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3975 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3976 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3993 u32 wptr, tmp; in r600_get_ih_wptr() local
4009 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4010 tmp |= IH_WPTR_OVERFLOW_CLEAR; in r600_get_ih_wptr()
4011 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
4344 u32 tmp; in r600_mmio_hdp_flush() local
4347 tmp = readl((void __iomem *)ptr); in r600_mmio_hdp_flush()
4444 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4520 tmp = RREG32(0x541c); in r600_pcie_gen2_enable()
4521 WREG32(0x541c, tmp | 0x8); in r600_pcie_gen2_enable()