Lines Matching refs:ring
1909 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r600_gfx_is_lockup() argument
1916 radeon_ring_lockup_update(rdev, ring); in r600_gfx_is_lockup()
1919 return radeon_ring_test_lockup(rdev, ring); in r600_gfx_is_lockup()
2417 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2612 struct radeon_ring *ring) in r600_gfx_get_rptr() argument
2617 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2625 struct radeon_ring *ring) in r600_gfx_get_wptr() argument
2635 struct radeon_ring *ring) in r600_gfx_set_wptr() argument
2637 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2685 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start() local
2689 r = radeon_ring_lock(rdev, ring, 7); in r600_cp_start()
2694 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2695 radeon_ring_write(ring, 0x1); in r600_cp_start()
2697 radeon_ring_write(ring, 0x0); in r600_cp_start()
2698 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2700 radeon_ring_write(ring, 0x3); in r600_cp_start()
2701 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2703 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2704 radeon_ring_write(ring, 0); in r600_cp_start()
2705 radeon_ring_write(ring, 0); in r600_cp_start()
2706 radeon_ring_unlock_commit(rdev, ring, false); in r600_cp_start()
2715 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume() local
2727 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2741 ring->wptr = 0; in r600_cp_resume()
2742 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2760 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2764 ring->ready = true; in r600_cp_resume()
2765 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2767 ring->ready = false; in r600_cp_resume()
2777 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) in r600_ring_init() argument
2785 ring->ring_size = ring_size; in r600_ring_init()
2786 ring->align_mask = 16 - 1; in r600_ring_init()
2788 if (radeon_ring_supports_scratch_reg(rdev, ring)) { in r600_ring_init()
2789 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2792 ring->rptr_save_reg = 0; in r600_ring_init()
2799 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini() local
2801 radeon_ring_fini(rdev, ring); in r600_cp_fini()
2802 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2820 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ring_test() argument
2833 r = radeon_ring_lock(rdev, ring, 3); in r600_ring_test()
2835 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in r600_ring_test()
2839 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2840 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2841 radeon_ring_write(ring, 0xDEADBEEF); in r600_ring_test()
2842 radeon_ring_unlock_commit(rdev, ring, false); in r600_ring_test()
2850 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in r600_ring_test()
2853 ring->idx, scratch, tmp); in r600_ring_test()
2867 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit() local
2875 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2877 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2878 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2879 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2880 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2881 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2883 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2884 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()
2885 radeon_ring_write(ring, lower_32_bits(addr)); in r600_fence_ring_emit()
2886 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
2887 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2888 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2891 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2892 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2893 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2895 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2896 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2897 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2900 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2901 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); in r600_fence_ring_emit()
2903 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2904 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2905 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2907 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
2908 radeon_ring_write(ring, RB_INT_STAT); in r600_fence_ring_emit()
2924 struct radeon_ring *ring, in r600_semaphore_ring_emit() argument
2934 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2935 radeon_ring_write(ring, lower_32_bits(addr)); in r600_semaphore_ring_emit()
2936 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); in r600_semaphore_ring_emit()
2941 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
2942 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
2969 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma() local
2978 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); in r600_copy_cpdma()
2986 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
2988 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2989 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2990 radeon_ring_write(ring, WAIT_3D_IDLE_bit); in r600_copy_cpdma()
2999 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma()
3000 radeon_ring_write(ring, lower_32_bits(src_offset)); in r600_copy_cpdma()
3001 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
3002 radeon_ring_write(ring, lower_32_bits(dst_offset)); in r600_copy_cpdma()
3003 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in r600_copy_cpdma()
3004 radeon_ring_write(ring, cur_size_in_bytes); in r600_copy_cpdma()
3008 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
3009 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
3010 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); in r600_copy_cpdma()
3012 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
3014 radeon_ring_unlock_undo(rdev, ring); in r600_copy_cpdma()
3019 radeon_ring_unlock_commit(rdev, ring, false); in r600_copy_cpdma()
3040 struct radeon_ring *ring; in r600_startup() local
3082 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_startup()
3100 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3101 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3114 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_startup()
3115 if (ring->ring_size) { in r600_startup()
3116 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in r600_startup()
3264 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3265 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3270 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_init()
3271 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_init()
3328 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute() local
3331 if (ring->rptr_save_reg) { in r600_ring_ib_execute()
3332 next_rptr = ring->wptr + 3 + 4; in r600_ring_ib_execute()
3333 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_ib_execute()
3334 radeon_ring_write(ring, ((ring->rptr_save_reg - in r600_ring_ib_execute()
3336 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3338 next_rptr = ring->wptr + 5 + 4; in r600_ring_ib_execute()
3339 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute()
3340 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_ring_ib_execute()
3341 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
3342 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3343 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
3346 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in r600_ring_ib_execute()
3347 radeon_ring_write(ring, in r600_ring_ib_execute()
3352 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
3353 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()
3356 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ib_test() argument
3370 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3396 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in r600_ib_test()
3458 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3479 rdev->ih.ring = NULL; in r600_ih_ring_fini()
4082 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4083 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()