1610 	u32 reset_mask = 0;  in r600_gpu_check_soft_reset()  local
1621 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1628 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1633 		reset_mask |= RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1636 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1641 		reset_mask |= RADEON_RESET_DMA;  in r600_gpu_check_soft_reset()
1646 		reset_mask |= RADEON_RESET_RLC;  in r600_gpu_check_soft_reset()
1649 		reset_mask |= RADEON_RESET_IH;  in r600_gpu_check_soft_reset()
1652 		reset_mask |= RADEON_RESET_SEM;  in r600_gpu_check_soft_reset()
1655 		reset_mask |= RADEON_RESET_GRBM;  in r600_gpu_check_soft_reset()
1658 		reset_mask |= RADEON_RESET_VMC;  in r600_gpu_check_soft_reset()
1663 		reset_mask |= RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1666 		reset_mask |= RADEON_RESET_DISPLAY;  in r600_gpu_check_soft_reset()
1669 	if (reset_mask & RADEON_RESET_MC) {  in r600_gpu_check_soft_reset()
1670 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in r600_gpu_check_soft_reset()
1671 		reset_mask &= ~RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1674 	return reset_mask;  in r600_gpu_check_soft_reset()
1677 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in r600_gpu_soft_reset()  argument
1683 	if (reset_mask == 0)  in r600_gpu_soft_reset()
1686 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in r600_gpu_soft_reset()
1699 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1713 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in r600_gpu_soft_reset()
1742 	if (reset_mask & RADEON_RESET_CP) {  in r600_gpu_soft_reset()
1749 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1756 	if (reset_mask & RADEON_RESET_RLC)  in r600_gpu_soft_reset()
1759 	if (reset_mask & RADEON_RESET_SEM)  in r600_gpu_soft_reset()
1762 	if (reset_mask & RADEON_RESET_IH)  in r600_gpu_soft_reset()
1765 	if (reset_mask & RADEON_RESET_GRBM)  in r600_gpu_soft_reset()
1769 		if (reset_mask & RADEON_RESET_MC)  in r600_gpu_soft_reset()
1773 	if (reset_mask & RADEON_RESET_VMC)  in r600_gpu_soft_reset()
1876 	u32 reset_mask;  in r600_asic_reset()  local
1878 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1880 	if (reset_mask)  in r600_asic_reset()
1884 	r600_gpu_soft_reset(rdev, reset_mask);  in r600_asic_reset()
1886 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1889 	if (reset_mask && radeon_hard_reset)  in r600_asic_reset()
1892 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1894 	if (!reset_mask)  in r600_asic_reset()
1911 	u32 reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_gfx_is_lockup()  local
1913 	if (!(reset_mask & (RADEON_RESET_GFX |  in r600_gfx_is_lockup()