Lines Matching refs:rdev
100 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
103 int r600_mc_wait_for_idle(struct radeon_device *rdev);
104 static void r600_gpu_init(struct radeon_device *rdev);
105 void r600_fini(struct radeon_device *rdev);
106 void r600_irq_disable(struct radeon_device *rdev);
107 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
108 extern int evergreen_rlc_resume(struct radeon_device *rdev);
109 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
114 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) in r600_rcu_rreg() argument
119 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
122 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
126 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_rcu_wreg() argument
130 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
133 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
136 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) in r600_uvd_ctx_rreg() argument
141 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
144 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
148 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_uvd_ctx_wreg() argument
152 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
155 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
168 int r600_get_allowed_info_register(struct radeon_device *rdev, in r600_get_allowed_info_register() argument
192 u32 r600_get_xclk(struct radeon_device *rdev) in r600_get_xclk() argument
194 return rdev->clock.spll.reference_freq; in r600_get_xclk()
197 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in r600_set_uvd_clocks() argument
211 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
221 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
226 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in r600_set_uvd_clocks()
232 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) in r600_set_uvd_clocks()
237 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
245 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
273 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
276 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
293 struct radeon_device *rdev = dev->dev_private; in dce3_program_fmt() local
344 int rv6xx_get_temp(struct radeon_device *rdev) in rv6xx_get_temp() argument
356 void r600_pm_get_dynpm_state(struct radeon_device *rdev) in r600_pm_get_dynpm_state() argument
360 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
361 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
364 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { in r600_pm_get_dynpm_state()
367 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
370 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
372 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
373 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
374 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
377 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
378 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
379 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
381 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
382 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
383 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
385 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
386 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
387 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
390 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
395 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
396 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
397 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
399 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
400 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
403 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
405 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
406 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
407 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
409 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
413 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
414 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
415 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
417 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
418 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
419 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
421 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
422 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
423 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
426 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
431 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
432 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
434 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
437 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
438 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
439 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
450 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
451 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
453 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
454 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
456 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
457 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
458 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
463 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
464 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
466 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
468 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
470 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
471 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
474 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
475 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
476 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
477 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
479 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
480 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
482 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
483 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
486 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
487 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
488 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
490 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
494 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
495 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
496 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
497 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
498 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
500 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
501 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
503 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
504 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
505 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
509 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
510 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
511 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
521 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
522 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
523 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
524 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
525 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
529 void rs780_pm_init_profile(struct radeon_device *rdev) in rs780_pm_init_profile() argument
531 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
533 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
534 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
535 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
536 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
538 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
539 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
540 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
541 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
543 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
544 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
545 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
546 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
550 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
551 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
554 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
555 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
561 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
563 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
565 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
567 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
569 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
570 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
571 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
572 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
574 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
575 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
576 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
577 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
579 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
580 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
581 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
582 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
584 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
585 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
586 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
587 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
589 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
590 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
591 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
592 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
594 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
595 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
596 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
597 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
599 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
600 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
601 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
602 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
605 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
606 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
607 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
608 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
610 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
611 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
612 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
613 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
615 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
616 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
617 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
618 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
620 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
621 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
622 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
623 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
625 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
626 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
627 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
628 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
630 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
631 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
632 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
633 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
635 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
636 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
637 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
638 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
642 void r600_pm_init_profile(struct radeon_device *rdev) in r600_pm_init_profile() argument
646 if (rdev->family == CHIP_R600) { in r600_pm_init_profile()
649 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
650 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
651 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
652 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
654 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
655 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
656 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
657 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
659 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
660 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
661 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
662 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
664 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
665 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
666 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
667 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
669 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
670 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
671 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
672 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
674 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
675 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
676 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
677 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
679 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
680 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
681 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
682 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
684 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
686 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
687 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
688 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
689 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
691 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
692 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
693 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
694 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
696 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
697 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
698 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
699 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
701 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
702 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
703 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
704 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
706 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
707 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
708 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
709 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
711 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
712 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
713 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
714 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
716 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
717 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
718 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
719 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
722 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
723 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
724 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
725 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
727 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
728 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in r600_pm_init_profile()
730 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
731 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
732 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
733 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
734 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
736 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
737 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
738 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
739 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
741 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
742 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
743 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
744 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
745 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
747 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
748 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); in r600_pm_init_profile()
750 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
751 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
752 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
753 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
754 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
756 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
757 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
758 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
759 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
761 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
762 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
763 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
764 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
765 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
770 void r600_pm_misc(struct radeon_device *rdev) in r600_pm_misc() argument
772 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
773 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
774 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
781 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
782 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in r600_pm_misc()
783 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
789 bool r600_gui_idle(struct radeon_device *rdev) in r600_gui_idle() argument
798 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in r600_hpd_sense() argument
802 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_sense()
853 void r600_hpd_set_polarity(struct radeon_device *rdev, in r600_hpd_set_polarity() argument
857 bool connected = r600_hpd_sense(rdev, hpd); in r600_hpd_set_polarity()
859 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_set_polarity()
945 void r600_hpd_init(struct radeon_device *rdev) in r600_hpd_init() argument
947 struct drm_device *dev = rdev->ddev; in r600_hpd_init()
962 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_init()
964 if (ASIC_IS_DCE32(rdev)) in r600_hpd_init()
1006 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
1008 radeon_irq_kms_enable_hpd(rdev, enable); in r600_hpd_init()
1011 void r600_hpd_fini(struct radeon_device *rdev) in r600_hpd_fini() argument
1013 struct drm_device *dev = rdev->ddev; in r600_hpd_fini()
1019 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_fini()
1060 radeon_irq_kms_disable_hpd(rdev, disable); in r600_hpd_fini()
1066 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) in r600_pcie_gart_tlb_flush() argument
1072 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_pcie_gart_tlb_flush()
1073 !(rdev->flags & RADEON_IS_AGP)) { in r600_pcie_gart_tlb_flush()
1074 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1087 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1088 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1090 for (i = 0; i < rdev->usec_timeout; i++) { in r600_pcie_gart_tlb_flush()
1105 int r600_pcie_gart_init(struct radeon_device *rdev) in r600_pcie_gart_init() argument
1109 if (rdev->gart.robj) { in r600_pcie_gart_init()
1114 r = radeon_gart_init(rdev); in r600_pcie_gart_init()
1117 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1118 return radeon_gart_table_vram_alloc(rdev); in r600_pcie_gart_init()
1121 static int r600_pcie_gart_enable(struct radeon_device *rdev) in r600_pcie_gart_enable() argument
1126 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1127 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
1130 r = radeon_gart_table_vram_pin(rdev); in r600_pcie_gart_enable()
1161 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1162 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1163 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1167 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
1171 r600_pcie_gart_tlb_flush(rdev); in r600_pcie_gart_enable()
1173 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1174 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1175 rdev->gart.ready = true; in r600_pcie_gart_enable()
1179 static void r600_pcie_gart_disable(struct radeon_device *rdev) in r600_pcie_gart_disable() argument
1211 radeon_gart_table_vram_unpin(rdev); in r600_pcie_gart_disable()
1214 static void r600_pcie_gart_fini(struct radeon_device *rdev) in r600_pcie_gart_fini() argument
1216 radeon_gart_fini(rdev); in r600_pcie_gart_fini()
1217 r600_pcie_gart_disable(rdev); in r600_pcie_gart_fini()
1218 radeon_gart_table_vram_free(rdev); in r600_pcie_gart_fini()
1221 static void r600_agp_enable(struct radeon_device *rdev) in r600_agp_enable() argument
1255 int r600_mc_wait_for_idle(struct radeon_device *rdev) in r600_mc_wait_for_idle() argument
1260 for (i = 0; i < rdev->usec_timeout; i++) { in r600_mc_wait_for_idle()
1270 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs780_mc_rreg() argument
1275 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1279 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1283 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs780_mc_wreg() argument
1287 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1292 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1295 static void r600_mc_program(struct radeon_device *rdev) in r600_mc_program() argument
1311 rv515_mc_stop(rdev, &save); in r600_mc_program()
1312 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1313 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1318 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1319 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1322 rdev->mc.vram_start >> 12); in r600_mc_program()
1324 rdev->mc.gtt_end >> 12); in r600_mc_program()
1328 rdev->mc.gtt_start >> 12); in r600_mc_program()
1330 rdev->mc.vram_end >> 12); in r600_mc_program()
1333 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1334 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1336 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1340 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1343 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1344 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1345 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1346 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1352 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1355 rv515_mc_resume(rdev, &save); in r600_mc_program()
1358 rv515_vga_render_disable(rdev); in r600_mc_program()
1382 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r600_vram_gtt_location() argument
1388 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1392 if (rdev->flags & RADEON_IS_AGP) { in r600_vram_gtt_location()
1397 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1404 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1411 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r600_vram_gtt_location()
1416 if (rdev->flags & RADEON_IS_IGP) { in r600_vram_gtt_location()
1420 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1421 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1422 radeon_gtt_location(rdev, mc); in r600_vram_gtt_location()
1426 static int r600_mc_init(struct radeon_device *rdev) in r600_mc_init() argument
1434 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1459 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1461 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1462 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1464 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1465 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1466 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1467 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1469 if (rdev->flags & RADEON_IS_IGP) { in r600_mc_init()
1470 rs690_pm_info(rdev); in r600_mc_init()
1471 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1473 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { in r600_mc_init()
1475 rdev->fastfb_working = false; in r600_mc_init()
1480 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1486 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1488 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1489 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
1490 rdev->fastfb_working = true; in r600_mc_init()
1496 radeon_update_bandwidth_info(rdev); in r600_mc_init()
1500 int r600_vram_scratch_init(struct radeon_device *rdev) in r600_vram_scratch_init() argument
1504 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1505 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, in r600_vram_scratch_init()
1507 0, NULL, NULL, &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1513 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1516 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1517 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1519 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1522 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1523 (void **)&rdev->vram_scratch.ptr); in r600_vram_scratch_init()
1525 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1526 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1531 void r600_vram_scratch_fini(struct radeon_device *rdev) in r600_vram_scratch_fini() argument
1535 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1538 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1540 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1541 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1542 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1544 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1547 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) in r600_set_bios_scratch_engine_hung() argument
1559 static void r600_print_gpu_status_regs(struct radeon_device *rdev) in r600_print_gpu_status_regs() argument
1561 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1563 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", in r600_print_gpu_status_regs()
1565 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1567 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in r600_print_gpu_status_regs()
1569 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in r600_print_gpu_status_regs()
1571 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1573 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1575 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in r600_print_gpu_status_regs()
1579 static bool r600_is_display_hung(struct radeon_device *rdev) in r600_is_display_hung() argument
1585 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1593 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1608 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) in r600_gpu_check_soft_reset() argument
1615 if (rdev->family >= CHIP_RV770) { in r600_gpu_check_soft_reset()
1665 if (r600_is_display_hung(rdev)) in r600_gpu_check_soft_reset()
1677 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in r600_gpu_soft_reset() argument
1686 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1688 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1691 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1708 rv515_mc_stop(rdev, &save); in r600_gpu_soft_reset()
1709 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_soft_reset()
1710 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1714 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1750 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1768 if (!(rdev->flags & RADEON_IS_IGP)) { in r600_gpu_soft_reset()
1779 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1793 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1807 rv515_mc_resume(rdev, &save); in r600_gpu_soft_reset()
1810 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1813 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) in r600_gpu_pci_config_reset() argument
1818 dev_info(rdev->dev, "GPU pci config reset\n"); in r600_gpu_pci_config_reset()
1823 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1839 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1840 rv770_set_clk_bypass_mode(rdev); in r600_gpu_pci_config_reset()
1842 pci_clear_master(rdev->pdev); in r600_gpu_pci_config_reset()
1844 rv515_mc_stop(rdev, &save); in r600_gpu_pci_config_reset()
1845 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_pci_config_reset()
1846 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_pci_config_reset()
1857 radeon_pci_config_reset(rdev); in r600_gpu_pci_config_reset()
1867 for (i = 0; i < rdev->usec_timeout; i++) { in r600_gpu_pci_config_reset()
1874 int r600_asic_reset(struct radeon_device *rdev) in r600_asic_reset() argument
1878 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1881 r600_set_bios_scratch_engine_hung(rdev, true); in r600_asic_reset()
1884 r600_gpu_soft_reset(rdev, reset_mask); in r600_asic_reset()
1886 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1890 r600_gpu_pci_config_reset(rdev); in r600_asic_reset()
1892 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1895 r600_set_bios_scratch_engine_hung(rdev, false); in r600_asic_reset()
1909 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r600_gfx_is_lockup() argument
1911 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_gfx_is_lockup()
1916 radeon_ring_lockup_update(rdev, ring); in r600_gfx_is_lockup()
1919 return radeon_ring_test_lockup(rdev, ring); in r600_gfx_is_lockup()
1922 u32 r6xx_remap_render_backend(struct radeon_device *rdev, in r6xx_remap_render_backend() argument
1946 if (rdev->family <= CHIP_RV740) { in r6xx_remap_render_backend()
1977 static void r600_gpu_init(struct radeon_device *rdev) in r600_gpu_init() argument
1992 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1993 switch (rdev->family) { in r600_gpu_init()
1995 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1996 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1997 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1998 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1999 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
2000 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2001 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2002 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2003 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2004 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2005 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2006 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2007 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2011 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
2012 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
2013 rdev->config.r600.max_simds = 3; in r600_gpu_init()
2014 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2015 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2016 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2017 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2018 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2019 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2020 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2021 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2022 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2023 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2029 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
2030 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
2031 rdev->config.r600.max_simds = 2; in r600_gpu_init()
2032 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2033 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2034 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2035 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2036 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
2037 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2038 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2039 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2040 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2041 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
2044 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2045 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
2046 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2047 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2048 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2049 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2050 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2051 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2052 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2053 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2054 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2055 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2056 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2076 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2092 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2093 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2108 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2110 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2114 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2118 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2122 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2125 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2127 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2144 if (rdev->family == CHIP_RV670) in r600_gpu_init()
2149 if ((rdev->family > CHIP_R600)) in r600_gpu_init()
2153 if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2154 ((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2155 ((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2156 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2157 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2158 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2173 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2174 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2175 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2176 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2181 } else if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2182 ((rdev->family) == CHIP_RV630)) { in r600_gpu_init()
2203 if ((rdev->family) == CHIP_R600) { in r600_gpu_init()
2217 } else if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2218 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2219 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2220 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2237 } else if (((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2238 ((rdev->family) == CHIP_RV635)) { in r600_gpu_init()
2252 } else if ((rdev->family) == CHIP_RV670) { in r600_gpu_init()
2275 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2276 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2277 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2278 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2301 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2302 switch (rdev->family) { in r600_gpu_init()
2345 switch (rdev->family) { in r600_gpu_init()
2383 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) in r600_pciep_rreg() argument
2388 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2392 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2396 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_pciep_wreg() argument
2400 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2405 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2411 void r600_cp_stop(struct radeon_device *rdev) in r600_cp_stop() argument
2413 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_stop()
2414 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2417 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2420 int r600_init_microcode(struct radeon_device *rdev) in r600_init_microcode() argument
2431 switch (rdev->family) { in r600_init_microcode()
2525 if (rdev->family >= CHIP_CEDAR) { in r600_init_microcode()
2529 } else if (rdev->family >= CHIP_RV770) { in r600_init_microcode()
2542 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in r600_init_microcode()
2545 if (rdev->pfp_fw->size != pfp_req_size) { in r600_init_microcode()
2548 rdev->pfp_fw->size, fw_name); in r600_init_microcode()
2554 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r600_init_microcode()
2557 if (rdev->me_fw->size != me_req_size) { in r600_init_microcode()
2560 rdev->me_fw->size, fw_name); in r600_init_microcode()
2565 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in r600_init_microcode()
2568 if (rdev->rlc_fw->size != rlc_req_size) { in r600_init_microcode()
2571 rdev->rlc_fw->size, fw_name); in r600_init_microcode()
2575 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { in r600_init_microcode()
2577 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in r600_init_microcode()
2582 release_firmware(rdev->smc_fw); in r600_init_microcode()
2583 rdev->smc_fw = NULL; in r600_init_microcode()
2585 } else if (rdev->smc_fw->size != smc_req_size) { in r600_init_microcode()
2588 rdev->smc_fw->size, fw_name); in r600_init_microcode()
2599 release_firmware(rdev->pfp_fw); in r600_init_microcode()
2600 rdev->pfp_fw = NULL; in r600_init_microcode()
2601 release_firmware(rdev->me_fw); in r600_init_microcode()
2602 rdev->me_fw = NULL; in r600_init_microcode()
2603 release_firmware(rdev->rlc_fw); in r600_init_microcode()
2604 rdev->rlc_fw = NULL; in r600_init_microcode()
2605 release_firmware(rdev->smc_fw); in r600_init_microcode()
2606 rdev->smc_fw = NULL; in r600_init_microcode()
2611 u32 r600_gfx_get_rptr(struct radeon_device *rdev, in r600_gfx_get_rptr() argument
2616 if (rdev->wb.enabled) in r600_gfx_get_rptr()
2617 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2624 u32 r600_gfx_get_wptr(struct radeon_device *rdev, in r600_gfx_get_wptr() argument
2634 void r600_gfx_set_wptr(struct radeon_device *rdev, in r600_gfx_set_wptr() argument
2641 static int r600_cp_load_microcode(struct radeon_device *rdev) in r600_cp_load_microcode() argument
2646 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2649 r600_cp_stop(rdev); in r600_cp_load_microcode()
2665 fw_data = (const __be32 *)rdev->me_fw->data; in r600_cp_load_microcode()
2671 fw_data = (const __be32 *)rdev->pfp_fw->data; in r600_cp_load_microcode()
2683 int r600_cp_start(struct radeon_device *rdev) in r600_cp_start() argument
2685 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2689 r = radeon_ring_lock(rdev, ring, 7); in r600_cp_start()
2696 if (rdev->family >= CHIP_RV770) { in r600_cp_start()
2698 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2701 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2706 radeon_ring_unlock_commit(rdev, ring, false); in r600_cp_start()
2713 int r600_cp_resume(struct radeon_device *rdev) in r600_cp_resume() argument
2715 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2746 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2747 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2748 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2750 if (rdev->wb.enabled) in r600_cp_resume()
2763 r600_cp_start(rdev); in r600_cp_resume()
2765 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2771 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_resume()
2772 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()
2777 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) in r600_ring_init() argument
2788 if (radeon_ring_supports_scratch_reg(rdev, ring)) { in r600_ring_init()
2789 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2797 void r600_cp_fini(struct radeon_device *rdev) in r600_cp_fini() argument
2799 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini()
2800 r600_cp_stop(rdev); in r600_cp_fini()
2801 radeon_ring_fini(rdev, ring); in r600_cp_fini()
2802 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2808 void r600_scratch_init(struct radeon_device *rdev) in r600_scratch_init() argument
2812 rdev->scratch.num_reg = 7; in r600_scratch_init()
2813 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2814 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2815 rdev->scratch.free[i] = true; in r600_scratch_init()
2816 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2820 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ring_test() argument
2827 r = radeon_scratch_get(rdev, &scratch); in r600_ring_test()
2833 r = radeon_ring_lock(rdev, ring, 3); in r600_ring_test()
2836 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2842 radeon_ring_unlock_commit(rdev, ring, false); in r600_ring_test()
2843 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ring_test()
2849 if (i < rdev->usec_timeout) { in r600_ring_test()
2856 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2864 void r600_fence_ring_emit(struct radeon_device *rdev, in r600_fence_ring_emit() argument
2867 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit()
2871 if (rdev->family >= CHIP_RV770) in r600_fence_ring_emit()
2874 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2875 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2904 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2923 bool r600_semaphore_ring_emit(struct radeon_device *rdev, in r600_semaphore_ring_emit() argument
2931 if (rdev->family < CHIP_CAYMAN) in r600_semaphore_ring_emit()
2939 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { in r600_semaphore_ring_emit()
2961 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, in r600_copy_cpdma() argument
2968 int ring_index = rdev->asic->copy.blit_ring_index; in r600_copy_cpdma()
2969 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma()
2978 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); in r600_copy_cpdma()
2981 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
2985 radeon_sync_resv(rdev, &sync, resv, false); in r600_copy_cpdma()
2986 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
3012 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
3014 radeon_ring_unlock_undo(rdev, ring); in r600_copy_cpdma()
3015 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
3019 radeon_ring_unlock_commit(rdev, ring, false); in r600_copy_cpdma()
3020 radeon_sync_free(rdev, &sync, fence); in r600_copy_cpdma()
3025 int r600_set_surface_reg(struct radeon_device *rdev, int reg, in r600_set_surface_reg() argument
3033 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) in r600_clear_surface_reg() argument
3038 static int r600_startup(struct radeon_device *rdev) in r600_startup() argument
3044 r600_pcie_gen2_enable(rdev); in r600_startup()
3047 r = r600_vram_scratch_init(rdev); in r600_startup()
3051 r600_mc_program(rdev); in r600_startup()
3053 if (rdev->flags & RADEON_IS_AGP) { in r600_startup()
3054 r600_agp_enable(rdev); in r600_startup()
3056 r = r600_pcie_gart_enable(rdev); in r600_startup()
3060 r600_gpu_init(rdev); in r600_startup()
3063 r = radeon_wb_init(rdev); in r600_startup()
3067 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_startup()
3069 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
3073 if (rdev->has_uvd) { in r600_startup()
3074 r = uvd_v1_0_resume(rdev); in r600_startup()
3076 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in r600_startup()
3078 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in r600_startup()
3082 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_startup()
3086 if (!rdev->irq.installed) { in r600_startup()
3087 r = radeon_irq_kms_init(rdev); in r600_startup()
3092 r = r600_irq_init(rdev); in r600_startup()
3095 radeon_irq_kms_fini(rdev); in r600_startup()
3098 r600_irq_set(rdev); in r600_startup()
3100 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3101 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3106 r = r600_cp_load_microcode(rdev); in r600_startup()
3109 r = r600_cp_resume(rdev); in r600_startup()
3113 if (rdev->has_uvd) { in r600_startup()
3114 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_startup()
3116 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in r600_startup()
3119 r = uvd_v1_0_init(rdev); in r600_startup()
3125 r = radeon_ib_pool_init(rdev); in r600_startup()
3127 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_startup()
3131 r = radeon_audio_init(rdev); in r600_startup()
3140 void r600_vga_set_state(struct radeon_device *rdev, bool state) in r600_vga_set_state() argument
3154 int r600_resume(struct radeon_device *rdev) in r600_resume() argument
3163 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
3165 if (rdev->pm.pm_method == PM_METHOD_DPM) in r600_resume()
3166 radeon_pm_resume(rdev); in r600_resume()
3168 rdev->accel_working = true; in r600_resume()
3169 r = r600_startup(rdev); in r600_resume()
3172 rdev->accel_working = false; in r600_resume()
3179 int r600_suspend(struct radeon_device *rdev) in r600_suspend() argument
3181 radeon_pm_suspend(rdev); in r600_suspend()
3182 radeon_audio_fini(rdev); in r600_suspend()
3183 r600_cp_stop(rdev); in r600_suspend()
3184 if (rdev->has_uvd) { in r600_suspend()
3185 uvd_v1_0_fini(rdev); in r600_suspend()
3186 radeon_uvd_suspend(rdev); in r600_suspend()
3188 r600_irq_suspend(rdev); in r600_suspend()
3189 radeon_wb_disable(rdev); in r600_suspend()
3190 r600_pcie_gart_disable(rdev); in r600_suspend()
3201 int r600_init(struct radeon_device *rdev) in r600_init() argument
3205 if (r600_debugfs_mc_info_init(rdev)) { in r600_init()
3209 if (!radeon_get_bios(rdev)) { in r600_init()
3210 if (ASIC_IS_AVIVO(rdev)) in r600_init()
3214 if (!rdev->is_atom_bios) { in r600_init()
3215 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in r600_init()
3218 r = radeon_atombios_init(rdev); in r600_init()
3222 if (!radeon_card_posted(rdev)) { in r600_init()
3223 if (!rdev->bios) { in r600_init()
3224 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in r600_init()
3228 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
3231 r600_scratch_init(rdev); in r600_init()
3233 radeon_surface_init(rdev); in r600_init()
3235 radeon_get_clock_info(rdev->ddev); in r600_init()
3237 r = radeon_fence_driver_init(rdev); in r600_init()
3240 if (rdev->flags & RADEON_IS_AGP) { in r600_init()
3241 r = radeon_agp_init(rdev); in r600_init()
3243 radeon_agp_disable(rdev); in r600_init()
3245 r = r600_mc_init(rdev); in r600_init()
3249 r = radeon_bo_init(rdev); in r600_init()
3253 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_init()
3254 r = r600_init_microcode(rdev); in r600_init()
3262 radeon_pm_init(rdev); in r600_init()
3264 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3265 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3267 if (rdev->has_uvd) { in r600_init()
3268 r = radeon_uvd_init(rdev); in r600_init()
3270 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_init()
3271 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_init()
3275 rdev->ih.ring_obj = NULL; in r600_init()
3276 r600_ih_ring_init(rdev, 64 * 1024); in r600_init()
3278 r = r600_pcie_gart_init(rdev); in r600_init()
3282 rdev->accel_working = true; in r600_init()
3283 r = r600_startup(rdev); in r600_init()
3285 dev_err(rdev->dev, "disabling GPU acceleration\n"); in r600_init()
3286 r600_cp_fini(rdev); in r600_init()
3287 r600_irq_fini(rdev); in r600_init()
3288 radeon_wb_fini(rdev); in r600_init()
3289 radeon_ib_pool_fini(rdev); in r600_init()
3290 radeon_irq_kms_fini(rdev); in r600_init()
3291 r600_pcie_gart_fini(rdev); in r600_init()
3292 rdev->accel_working = false; in r600_init()
3298 void r600_fini(struct radeon_device *rdev) in r600_fini() argument
3300 radeon_pm_fini(rdev); in r600_fini()
3301 radeon_audio_fini(rdev); in r600_fini()
3302 r600_cp_fini(rdev); in r600_fini()
3303 r600_irq_fini(rdev); in r600_fini()
3304 if (rdev->has_uvd) { in r600_fini()
3305 uvd_v1_0_fini(rdev); in r600_fini()
3306 radeon_uvd_fini(rdev); in r600_fini()
3308 radeon_wb_fini(rdev); in r600_fini()
3309 radeon_ib_pool_fini(rdev); in r600_fini()
3310 radeon_irq_kms_fini(rdev); in r600_fini()
3311 r600_pcie_gart_fini(rdev); in r600_fini()
3312 r600_vram_scratch_fini(rdev); in r600_fini()
3313 radeon_agp_fini(rdev); in r600_fini()
3314 radeon_gem_fini(rdev); in r600_fini()
3315 radeon_fence_driver_fini(rdev); in r600_fini()
3316 radeon_bo_fini(rdev); in r600_fini()
3317 radeon_atombios_fini(rdev); in r600_fini()
3318 kfree(rdev->bios); in r600_fini()
3319 rdev->bios = NULL; in r600_fini()
3326 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in r600_ring_ib_execute() argument
3328 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute()
3337 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3356 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ib_test() argument
3364 r = radeon_scratch_get(rdev, &scratch); in r600_ib_test()
3370 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3379 r = radeon_ib_schedule(rdev, &ib, NULL, false); in r600_ib_test()
3389 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ib_test()
3395 if (i < rdev->usec_timeout) { in r600_ib_test()
3403 radeon_ib_free(rdev, &ib); in r600_ib_test()
3405 radeon_scratch_free(rdev, scratch); in r600_ib_test()
3420 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) in r600_ih_ring_init() argument
3427 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3428 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3429 rdev->ih.rptr = 0; in r600_ih_ring_init()
3432 int r600_ih_ring_alloc(struct radeon_device *rdev) in r600_ih_ring_alloc() argument
3437 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3438 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3441 NULL, NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3446 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3449 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3451 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
3453 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3457 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3458 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3459 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3468 void r600_ih_ring_fini(struct radeon_device *rdev) in r600_ih_ring_fini() argument
3471 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3472 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
3474 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
3475 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
3476 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
3478 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
3479 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3480 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
3484 void r600_rlc_stop(struct radeon_device *rdev) in r600_rlc_stop() argument
3487 if ((rdev->family >= CHIP_RV770) && in r600_rlc_stop()
3488 (rdev->family <= CHIP_RV740)) { in r600_rlc_stop()
3500 static void r600_rlc_start(struct radeon_device *rdev) in r600_rlc_start() argument
3505 static int r600_rlc_resume(struct radeon_device *rdev) in r600_rlc_resume() argument
3510 if (!rdev->rlc_fw) in r600_rlc_resume()
3513 r600_rlc_stop(rdev); in r600_rlc_resume()
3525 fw_data = (const __be32 *)rdev->rlc_fw->data; in r600_rlc_resume()
3526 if (rdev->family >= CHIP_RV770) { in r600_rlc_resume()
3539 r600_rlc_start(rdev); in r600_rlc_resume()
3544 static void r600_enable_interrupts(struct radeon_device *rdev) in r600_enable_interrupts() argument
3553 rdev->ih.enabled = true; in r600_enable_interrupts()
3556 void r600_disable_interrupts(struct radeon_device *rdev) in r600_disable_interrupts() argument
3568 rdev->ih.enabled = false; in r600_disable_interrupts()
3569 rdev->ih.rptr = 0; in r600_disable_interrupts()
3572 static void r600_disable_interrupt_state(struct radeon_device *rdev) in r600_disable_interrupt_state() argument
3583 if (ASIC_IS_DCE3(rdev)) { in r600_disable_interrupt_state()
3594 if (ASIC_IS_DCE32(rdev)) { in r600_disable_interrupt_state()
3625 int r600_irq_init(struct radeon_device *rdev) in r600_irq_init() argument
3632 ret = r600_ih_ring_alloc(rdev); in r600_irq_init()
3637 r600_disable_interrupts(rdev); in r600_irq_init()
3640 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3641 ret = evergreen_rlc_resume(rdev); in r600_irq_init()
3643 ret = r600_rlc_resume(rdev); in r600_irq_init()
3645 r600_ih_ring_fini(rdev); in r600_irq_init()
3651 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3661 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3662 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
3668 if (rdev->wb.enabled) in r600_irq_init()
3672 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3673 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3684 if (rdev->msi_enabled) in r600_irq_init()
3689 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3690 evergreen_disable_interrupt_state(rdev); in r600_irq_init()
3692 r600_disable_interrupt_state(rdev); in r600_irq_init()
3695 pci_set_master(rdev->pdev); in r600_irq_init()
3698 r600_enable_interrupts(rdev); in r600_irq_init()
3703 void r600_irq_suspend(struct radeon_device *rdev) in r600_irq_suspend() argument
3705 r600_irq_disable(rdev); in r600_irq_suspend()
3706 r600_rlc_stop(rdev); in r600_irq_suspend()
3709 void r600_irq_fini(struct radeon_device *rdev) in r600_irq_fini() argument
3711 r600_irq_suspend(rdev); in r600_irq_fini()
3712 r600_ih_ring_fini(rdev); in r600_irq_fini()
3715 int r600_irq_set(struct radeon_device *rdev) in r600_irq_set() argument
3725 if (!rdev->irq.installed) { in r600_irq_set()
3730 if (!rdev->ih.enabled) { in r600_irq_set()
3731 r600_disable_interrupts(rdev); in r600_irq_set()
3733 r600_disable_interrupt_state(rdev); in r600_irq_set()
3737 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3742 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3761 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3764 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3768 if (rdev->irq.dpm_thermal) { in r600_irq_set()
3773 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r600_irq_set()
3779 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in r600_irq_set()
3784 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3785 atomic_read(&rdev->irq.pflip[0])) { in r600_irq_set()
3789 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3790 atomic_read(&rdev->irq.pflip[1])) { in r600_irq_set()
3794 if (rdev->irq.hpd[0]) { in r600_irq_set()
3798 if (rdev->irq.hpd[1]) { in r600_irq_set()
3802 if (rdev->irq.hpd[2]) { in r600_irq_set()
3806 if (rdev->irq.hpd[3]) { in r600_irq_set()
3810 if (rdev->irq.hpd[4]) { in r600_irq_set()
3814 if (rdev->irq.hpd[5]) { in r600_irq_set()
3818 if (rdev->irq.afmt[0]) { in r600_irq_set()
3822 if (rdev->irq.afmt[1]) { in r600_irq_set()
3833 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3838 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3854 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3856 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3866 static void r600_irq_ack(struct radeon_device *rdev) in r600_irq_ack() argument
3870 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3871 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3872 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3873 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3874 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3875 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3876 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3878 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3879 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3882 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3883 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3884 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3885 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3886 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3888 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3889 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3891 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3893 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3895 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3897 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3899 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3901 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3903 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3904 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3914 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3915 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3925 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3926 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3936 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3941 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3942 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3947 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3952 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3957 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3963 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3968 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3969 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3982 void r600_irq_disable(struct radeon_device *rdev) in r600_irq_disable() argument
3984 r600_disable_interrupts(rdev); in r600_irq_disable()
3987 r600_irq_ack(rdev); in r600_irq_disable()
3988 r600_disable_interrupt_state(rdev); in r600_irq_disable()
3991 static u32 r600_get_ih_wptr(struct radeon_device *rdev) in r600_get_ih_wptr() argument
3995 if (rdev->wb.enabled) in r600_get_ih_wptr()
3996 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
4006 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in r600_get_ih_wptr()
4007 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4008 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
4013 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4046 int r600_irq_process(struct radeon_device *rdev) in r600_irq_process() argument
4056 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
4060 if (!rdev->msi_enabled) in r600_irq_process()
4063 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4067 if (atomic_xchg(&rdev->ih.lock, 1)) in r600_irq_process()
4070 rptr = rdev->ih.rptr; in r600_irq_process()
4077 r600_irq_ack(rdev); in r600_irq_process()
4082 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4083 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
4089 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4092 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
4093 drm_handle_vblank(rdev->ddev, 0); in r600_irq_process()
4094 rdev->pm.vblank_sync = true; in r600_irq_process()
4095 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4097 if (atomic_read(&rdev->irq.pflip[0])) in r600_irq_process()
4098 radeon_crtc_handle_vblank(rdev, 0); in r600_irq_process()
4099 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4104 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4107 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4119 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4122 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
4123 drm_handle_vblank(rdev->ddev, 1); in r600_irq_process()
4124 rdev->pm.vblank_sync = true; in r600_irq_process()
4125 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4127 if (atomic_read(&rdev->irq.pflip[1])) in r600_irq_process()
4128 radeon_crtc_handle_vblank(rdev, 1); in r600_irq_process()
4129 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4134 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4137 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4149 radeon_crtc_handle_flip(rdev, 0); in r600_irq_process()
4154 radeon_crtc_handle_flip(rdev, 1); in r600_irq_process()
4159 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4162 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4167 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4170 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4175 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4178 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4183 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4186 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4191 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4194 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4199 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4202 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4215 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4218 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4224 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4227 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4239 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in r600_irq_process()
4245 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4249 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4253 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in r600_irq_process()
4257 rdev->pm.dpm.thermal.high_to_low = false; in r600_irq_process()
4262 rdev->pm.dpm.thermal.high_to_low = true; in r600_irq_process()
4275 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
4279 schedule_delayed_work(&rdev->hotplug_work, 0); in r600_irq_process()
4281 schedule_work(&rdev->audio_work); in r600_irq_process()
4282 if (queue_thermal && rdev->pm.dpm_enabled) in r600_irq_process()
4283 schedule_work(&rdev->pm.dpm.thermal.work); in r600_irq_process()
4284 rdev->ih.rptr = rptr; in r600_irq_process()
4285 atomic_set(&rdev->ih.lock, 0); in r600_irq_process()
4288 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4304 struct radeon_device *rdev = dev->dev_private; in r600_debugfs_mc_info() local
4306 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); in r600_debugfs_mc_info()
4307 DREG32_SYS(m, rdev, VM_L2_STATUS); in r600_debugfs_mc_info()
4316 int r600_debugfs_mc_info_init(struct radeon_device *rdev) in r600_debugfs_mc_info_init() argument
4319 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); in r600_debugfs_mc_info_init()
4334 void r600_mmio_hdp_flush(struct radeon_device *rdev) in r600_mmio_hdp_flush() argument
4341 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_mmio_hdp_flush()
4342 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_mmio_hdp_flush()
4343 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; in r600_mmio_hdp_flush()
4352 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) in r600_set_pcie_lanes() argument
4356 if (rdev->flags & RADEON_IS_IGP) in r600_set_pcie_lanes()
4359 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_set_pcie_lanes()
4363 if (ASIC_IS_X2(rdev)) in r600_set_pcie_lanes()
4366 radeon_gui_idle(rdev); in r600_set_pcie_lanes()
4405 int r600_get_pcie_lanes(struct radeon_device *rdev) in r600_get_pcie_lanes() argument
4409 if (rdev->flags & RADEON_IS_IGP) in r600_get_pcie_lanes()
4412 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_get_pcie_lanes()
4416 if (ASIC_IS_X2(rdev)) in r600_get_pcie_lanes()
4419 radeon_gui_idle(rdev); in r600_get_pcie_lanes()
4442 static void r600_pcie_gen2_enable(struct radeon_device *rdev) in r600_pcie_gen2_enable() argument
4450 if (rdev->flags & RADEON_IS_IGP) in r600_pcie_gen2_enable()
4453 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_pcie_gen2_enable()
4457 if (ASIC_IS_X2(rdev)) in r600_pcie_gen2_enable()
4461 if (rdev->family <= CHIP_R600) in r600_pcie_gen2_enable()
4464 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in r600_pcie_gen2_enable()
4465 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in r600_pcie_gen2_enable()
4477 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4478 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4479 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4502 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4503 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4504 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4529 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4530 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4531 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4564 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) in r600_get_gpu_clock_counter() argument
4568 mutex_lock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()
4572 mutex_unlock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()