4354 	u32 link_width_cntl, mask;  in r600_set_pcie_lanes()  local
4396 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_set_pcie_lanes()
4397 	link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;  in r600_set_pcie_lanes()
4398 	link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;  in r600_set_pcie_lanes()
4399 	link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |  in r600_set_pcie_lanes()
4402 	WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_set_pcie_lanes()
4407 	u32 link_width_cntl;  in r600_get_pcie_lanes()  local
4421 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_get_pcie_lanes()
4423 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF…  in r600_get_pcie_lanes()
4444 	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;  in r600_pcie_gen2_enable()  local
4481 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4482 		link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4483 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4484 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4485 		if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {  in r600_pcie_gen2_enable()
4486 			lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;  in r600_pcie_gen2_enable()
4487 			link_width_cntl &= ~(LC_LINK_WIDTH_MASK |  in r600_pcie_gen2_enable()
4489 			link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;  in r600_pcie_gen2_enable()
4490 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4492 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4493 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4546 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4549 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4551 			link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4552 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()