120 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));  in r600_rcu_rreg()
131 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));  in r600_rcu_wreg()
132 	WREG32(R600_RCU_DATA, (v));  in r600_rcu_wreg()
142 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));  in r600_uvd_ctx_rreg()
153 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));  in r600_uvd_ctx_wreg()
154 	WREG32(R600_UVD_CTX_DATA, (v));  in r600_uvd_ctx_wreg()
340 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce3_program_fmt()
867 			WREG32(DC_HPD1_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
875 			WREG32(DC_HPD2_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
883 			WREG32(DC_HPD3_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
891 			WREG32(DC_HPD4_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
899 			WREG32(DC_HPD5_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
908 			WREG32(DC_HPD6_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
921 			WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
929 			WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
937 			WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);  in r600_hpd_set_polarity()
969 				WREG32(DC_HPD1_CONTROL, tmp);  in r600_hpd_init()
972 				WREG32(DC_HPD2_CONTROL, tmp);  in r600_hpd_init()
975 				WREG32(DC_HPD3_CONTROL, tmp);  in r600_hpd_init()
978 				WREG32(DC_HPD4_CONTROL, tmp);  in r600_hpd_init()
982 				WREG32(DC_HPD5_CONTROL, tmp);  in r600_hpd_init()
985 				WREG32(DC_HPD6_CONTROL, tmp);  in r600_hpd_init()
993 				WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);  in r600_hpd_init()
996 				WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);  in r600_hpd_init()
999 				WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);  in r600_hpd_init()
1022 				WREG32(DC_HPD1_CONTROL, 0);  in r600_hpd_fini()
1025 				WREG32(DC_HPD2_CONTROL, 0);  in r600_hpd_fini()
1028 				WREG32(DC_HPD3_CONTROL, 0);  in r600_hpd_fini()
1031 				WREG32(DC_HPD4_CONTROL, 0);  in r600_hpd_fini()
1035 				WREG32(DC_HPD5_CONTROL, 0);  in r600_hpd_fini()
1038 				WREG32(DC_HPD6_CONTROL, 0);  in r600_hpd_fini()
1046 				WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);  in r600_hpd_fini()
1049 				WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);  in r600_hpd_fini()
1052 				WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);  in r600_hpd_fini()
1082 		WREG32(HDP_DEBUG1, 0);  in r600_pcie_gart_tlb_flush()
1085 		WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);  in r600_pcie_gart_tlb_flush()
1087 	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);  in r600_pcie_gart_tlb_flush()
1088 	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);  in r600_pcie_gart_tlb_flush()
1089 	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));  in r600_pcie_gart_tlb_flush()
1135 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |  in r600_pcie_gart_enable()
1138 	WREG32(VM_L2_CNTL2, 0);  in r600_pcie_gart_enable()
1139 	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));  in r600_pcie_gart_enable()
1145 	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);  in r600_pcie_gart_enable()
1146 	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);  in r600_pcie_gart_enable()
1147 	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);  in r600_pcie_gart_enable()
1148 	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);  in r600_pcie_gart_enable()
1149 	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);  in r600_pcie_gart_enable()
1150 	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);  in r600_pcie_gart_enable()
1151 	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);  in r600_pcie_gart_enable()
1152 	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);  in r600_pcie_gart_enable()
1153 	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);  in r600_pcie_gart_enable()
1154 	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);  in r600_pcie_gart_enable()
1155 	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);  in r600_pcie_gart_enable()
1156 	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);  in r600_pcie_gart_enable()
1157 	WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);  in r600_pcie_gart_enable()
1158 	WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);  in r600_pcie_gart_enable()
1159 	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);  in r600_pcie_gart_enable()
1160 	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);  in r600_pcie_gart_enable()
1161 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in r600_pcie_gart_enable()
1162 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in r600_pcie_gart_enable()
1163 	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);  in r600_pcie_gart_enable()
1164 	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |  in r600_pcie_gart_enable()
1166 	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in r600_pcie_gart_enable()
1169 		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);  in r600_pcie_gart_enable()
1186 		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);  in r600_pcie_gart_disable()
1189 	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |  in r600_pcie_gart_disable()
1191 	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));  in r600_pcie_gart_disable()
1195 	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);  in r600_pcie_gart_disable()
1196 	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);  in r600_pcie_gart_disable()
1197 	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);  in r600_pcie_gart_disable()
1198 	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);  in r600_pcie_gart_disable()
1199 	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);  in r600_pcie_gart_disable()
1200 	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);  in r600_pcie_gart_disable()
1201 	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);  in r600_pcie_gart_disable()
1202 	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);  in r600_pcie_gart_disable()
1203 	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);  in r600_pcie_gart_disable()
1204 	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);  in r600_pcie_gart_disable()
1205 	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);  in r600_pcie_gart_disable()
1206 	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);  in r600_pcie_gart_disable()
1207 	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);  in r600_pcie_gart_disable()
1208 	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);  in r600_pcie_gart_disable()
1209 	WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);  in r600_pcie_gart_disable()
1210 	WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);  in r600_pcie_gart_disable()
1227 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |  in r600_agp_enable()
1230 	WREG32(VM_L2_CNTL2, 0);  in r600_agp_enable()
1231 	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));  in r600_agp_enable()
1237 	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);  in r600_agp_enable()
1238 	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);  in r600_agp_enable()
1239 	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);  in r600_agp_enable()
1240 	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);  in r600_agp_enable()
1241 	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);  in r600_agp_enable()
1242 	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);  in r600_agp_enable()
1243 	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);  in r600_agp_enable()
1244 	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);  in r600_agp_enable()
1245 	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);  in r600_agp_enable()
1246 	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);  in r600_agp_enable()
1247 	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);  in r600_agp_enable()
1248 	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);  in r600_agp_enable()
1249 	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);  in r600_agp_enable()
1250 	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);  in r600_agp_enable()
1252 		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);  in r600_agp_enable()
1276 	WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));  in rs780_mc_rreg()
1278 	WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);  in rs780_mc_rreg()
1288 	WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |  in rs780_mc_wreg()
1290 	WREG32(R_0028FC_MC_DATA, v);  in rs780_mc_wreg()
1291 	WREG32(R_0028F8_MC_INDEX, 0x7F);  in rs780_mc_wreg()
1303 		WREG32((0x2c14 + j), 0x00000000);  in r600_mc_program()
1304 		WREG32((0x2c18 + j), 0x00000000);  in r600_mc_program()
1305 		WREG32((0x2c1c + j), 0x00000000);  in r600_mc_program()
1306 		WREG32((0x2c20 + j), 0x00000000);  in r600_mc_program()
1307 		WREG32((0x2c24 + j), 0x00000000);  in r600_mc_program()
1309 	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);  in r600_mc_program()
1316 	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);  in r600_mc_program()
1321 			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,  in r600_mc_program()
1323 			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in r600_mc_program()
1327 			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,  in r600_mc_program()
1329 			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in r600_mc_program()
1333 		WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);  in r600_mc_program()
1334 		WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);  in r600_mc_program()
1336 	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);  in r600_mc_program()
1339 	WREG32(MC_VM_FB_LOCATION, tmp);  in r600_mc_program()
1340 	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));  in r600_mc_program()
1341 	WREG32(HDP_NONSURFACE_INFO, (2 << 7));  in r600_mc_program()
1342 	WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in r600_mc_program()
1344 		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);  in r600_mc_program()
1345 		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);  in r600_mc_program()
1346 		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);  in r600_mc_program()
1348 		WREG32(MC_VM_AGP_BASE, 0);  in r600_mc_program()
1349 		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);  in r600_mc_program()
1350 		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);  in r600_mc_program()
1556 	WREG32(R600_BIOS_3_SCRATCH, tmp);  in r600_set_bios_scratch_engine_hung()
1692 		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));  in r600_gpu_soft_reset()
1694 		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));  in r600_gpu_soft_reset()
1697 	WREG32(RLC_CNTL, 0);  in r600_gpu_soft_reset()
1703 		WREG32(DMA_RB_CNTL, tmp);  in r600_gpu_soft_reset()
1780 		WREG32(R_008020_GRBM_SOFT_RESET, tmp);  in r600_gpu_soft_reset()
1786 		WREG32(R_008020_GRBM_SOFT_RESET, tmp);  in r600_gpu_soft_reset()
1794 		WREG32(SRBM_SOFT_RESET, tmp);  in r600_gpu_soft_reset()
1800 		WREG32(SRBM_SOFT_RESET, tmp);  in r600_gpu_soft_reset()
1824 		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));  in r600_gpu_pci_config_reset()
1826 		WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));  in r600_gpu_pci_config_reset()
1829 	WREG32(RLC_CNTL, 0);  in r600_gpu_pci_config_reset()
1834 	WREG32(DMA_RB_CNTL, tmp);  in r600_gpu_pci_config_reset()
1852 	WREG32(BUS_CNTL, tmp);  in r600_gpu_pci_config_reset()
1862 	WREG32(SRBM_SOFT_RESET, tmp);  in r600_gpu_pci_config_reset()
1864 	WREG32(SRBM_SOFT_RESET, 0);  in r600_gpu_pci_config_reset()
2064 		WREG32((0x2c14 + j), 0x00000000);  in r600_gpu_init()
2065 		WREG32((0x2c18 + j), 0x00000000);  in r600_gpu_init()
2066 		WREG32((0x2c1c + j), 0x00000000);  in r600_gpu_init()
2067 		WREG32((0x2c20 + j), 0x00000000);  in r600_gpu_init()
2068 		WREG32((0x2c24 + j), 0x00000000);  in r600_gpu_init()
2071 	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));  in r600_gpu_init()
2128 	WREG32(GB_TILING_CONFIG, tiling_config);  in r600_gpu_init()
2129 	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);  in r600_gpu_init()
2130 	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);  in r600_gpu_init()
2131 	WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);  in r600_gpu_init()
2134 	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);  in r600_gpu_init()
2135 	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);  in r600_gpu_init()
2138 	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));  in r600_gpu_init()
2139 	WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));  in r600_gpu_init()
2141 	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |  in r600_gpu_init()
2145 		WREG32(ARB_GDEC_RD_CNTL, 0x00000021);  in r600_gpu_init()
2151 	WREG32(SX_DEBUG_1, tmp);  in r600_gpu_init()
2159 		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);  in r600_gpu_init()
2161 		WREG32(DB_DEBUG, 0);  in r600_gpu_init()
2163 	WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |  in r600_gpu_init()
2166 	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);  in r600_gpu_init()
2167 	WREG32(VGT_NUM_INSTANCES, 0);  in r600_gpu_init()
2169 	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));  in r600_gpu_init()
2170 	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));  in r600_gpu_init()
2186 	WREG32(SQ_MS_FIFO_SIZES, tmp);  in r600_gpu_init()
2268 	WREG32(SQ_CONFIG, sq_config);  in r600_gpu_init()
2269 	WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);  in r600_gpu_init()
2270 	WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);  in r600_gpu_init()
2271 	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);  in r600_gpu_init()
2272 	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);  in r600_gpu_init()
2273 	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);  in r600_gpu_init()
2279 		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));  in r600_gpu_init()
2281 		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));  in r600_gpu_init()
2285 	WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |  in r600_gpu_init()
2287 	WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |  in r600_gpu_init()
2291 	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |  in r600_gpu_init()
2295 	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |  in r600_gpu_init()
2300 	WREG32(VGT_STRMOUT_EN, 0);  in r600_gpu_init()
2318 	WREG32(VGT_ES_PER_GS, 128);  in r600_gpu_init()
2319 	WREG32(VGT_GS_PER_ES, tmp);  in r600_gpu_init()
2320 	WREG32(VGT_GS_PER_VS, 2);  in r600_gpu_init()
2321 	WREG32(VGT_GS_VERTEX_REUSE, 16);  in r600_gpu_init()
2324 	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);  in r600_gpu_init()
2325 	WREG32(VGT_STRMOUT_EN, 0);  in r600_gpu_init()
2326 	WREG32(SX_MISC, 0);  in r600_gpu_init()
2327 	WREG32(PA_SC_MODE_CNTL, 0);  in r600_gpu_init()
2328 	WREG32(PA_SC_AA_CONFIG, 0);  in r600_gpu_init()
2329 	WREG32(PA_SC_LINE_STIPPLE, 0);  in r600_gpu_init()
2330 	WREG32(SPI_INPUT_Z, 0);  in r600_gpu_init()
2331 	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));  in r600_gpu_init()
2332 	WREG32(CB_COLOR7_FRAG, 0);  in r600_gpu_init()
2335 	WREG32(CB_COLOR0_BASE, 0);  in r600_gpu_init()
2336 	WREG32(CB_COLOR1_BASE, 0);  in r600_gpu_init()
2337 	WREG32(CB_COLOR2_BASE, 0);  in r600_gpu_init()
2338 	WREG32(CB_COLOR3_BASE, 0);  in r600_gpu_init()
2339 	WREG32(CB_COLOR4_BASE, 0);  in r600_gpu_init()
2340 	WREG32(CB_COLOR5_BASE, 0);  in r600_gpu_init()
2341 	WREG32(CB_COLOR6_BASE, 0);  in r600_gpu_init()
2342 	WREG32(CB_COLOR7_BASE, 0);  in r600_gpu_init()
2343 	WREG32(CB_COLOR7_FRAG, 0);  in r600_gpu_init()
2363 	WREG32(TC_CNTL, tmp);  in r600_gpu_init()
2366 	WREG32(HDP_HOST_PATH_CNTL, tmp);  in r600_gpu_init()
2370 	WREG32(ARB_POP, tmp);  in r600_gpu_init()
2372 	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);  in r600_gpu_init()
2373 	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |  in r600_gpu_init()
2375 	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));  in r600_gpu_init()
2376 	WREG32(VC_ENHANCE, 0);  in r600_gpu_init()
2389 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));  in r600_pciep_rreg()
2401 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));  in r600_pciep_wreg()
2403 	WREG32(PCIE_PORT_DATA, (v));  in r600_pciep_wreg()
2415 	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));  in r600_cp_stop()
2416 	WREG32(SCRATCH_UMSK, 0);  in r600_cp_stop()
2637 	WREG32(R600_CP_RB_WPTR, ring->wptr);  in r600_gfx_set_wptr()
2651 	WREG32(CP_RB_CNTL,  in r600_cp_load_microcode()
2658 	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);  in r600_cp_load_microcode()
2661 	WREG32(GRBM_SOFT_RESET, 0);  in r600_cp_load_microcode()
2663 	WREG32(CP_ME_RAM_WADDR, 0);  in r600_cp_load_microcode()
2666 	WREG32(CP_ME_RAM_WADDR, 0);  in r600_cp_load_microcode()
2668 		WREG32(CP_ME_RAM_DATA,  in r600_cp_load_microcode()
2672 	WREG32(CP_PFP_UCODE_ADDR, 0);  in r600_cp_load_microcode()
2674 		WREG32(CP_PFP_UCODE_DATA,  in r600_cp_load_microcode()
2677 	WREG32(CP_PFP_UCODE_ADDR, 0);  in r600_cp_load_microcode()
2678 	WREG32(CP_ME_RAM_WADDR, 0);  in r600_cp_load_microcode()
2679 	WREG32(CP_ME_RAM_RADDR, 0);  in r600_cp_load_microcode()
2709 	WREG32(R_0086D8_CP_ME_CNTL, cp_me);  in r600_cp_start()
2721 	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);  in r600_cp_resume()
2724 	WREG32(GRBM_SOFT_RESET, 0);  in r600_cp_resume()
2732 	WREG32(CP_RB_CNTL, tmp);  in r600_cp_resume()
2733 	WREG32(CP_SEM_WAIT_TIMER, 0x0);  in r600_cp_resume()
2736 	WREG32(CP_RB_WPTR_DELAY, 0);  in r600_cp_resume()
2739 	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);  in r600_cp_resume()
2740 	WREG32(CP_RB_RPTR_WR, 0);  in r600_cp_resume()
2742 	WREG32(CP_RB_WPTR, ring->wptr);  in r600_cp_resume()
2745 	WREG32(CP_RB_RPTR_ADDR,  in r600_cp_resume()
2747 	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in r600_cp_resume()
2748 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in r600_cp_resume()
2751 		WREG32(SCRATCH_UMSK, 0xff);  in r600_cp_resume()
2754 		WREG32(SCRATCH_UMSK, 0);  in r600_cp_resume()
2758 	WREG32(CP_RB_CNTL, tmp);  in r600_cp_resume()
2760 	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);  in r600_cp_resume()
2761 	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));  in r600_cp_resume()
2832 	WREG32(scratch, 0xCAFEDEAD);  in r600_ring_test()
3151 	WREG32(CONFIG_CNTL, temp);  in r600_vga_set_state()
3369 	WREG32(scratch, 0xCAFEDEAD);  in r600_ib_test()
3490 		WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);  in r600_rlc_stop()
3493 		WREG32(SRBM_SOFT_RESET, 0);  in r600_rlc_stop()
3497 	WREG32(RLC_CNTL, 0);  in r600_rlc_stop()
3502 	WREG32(RLC_CNTL, RLC_ENABLE);  in r600_rlc_start()
3515 	WREG32(RLC_HB_CNTL, 0);  in r600_rlc_resume()
3517 	WREG32(RLC_HB_BASE, 0);  in r600_rlc_resume()
3518 	WREG32(RLC_HB_RPTR, 0);  in r600_rlc_resume()
3519 	WREG32(RLC_HB_WPTR, 0);  in r600_rlc_resume()
3520 	WREG32(RLC_HB_WPTR_LSB_ADDR, 0);  in r600_rlc_resume()
3521 	WREG32(RLC_HB_WPTR_MSB_ADDR, 0);  in r600_rlc_resume()
3522 	WREG32(RLC_MC_CNTL, 0);  in r600_rlc_resume()
3523 	WREG32(RLC_UCODE_CNTL, 0);  in r600_rlc_resume()
3528 			WREG32(RLC_UCODE_ADDR, i);  in r600_rlc_resume()
3529 			WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));  in r600_rlc_resume()
3533 			WREG32(RLC_UCODE_ADDR, i);  in r600_rlc_resume()
3534 			WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));  in r600_rlc_resume()
3537 	WREG32(RLC_UCODE_ADDR, 0);  in r600_rlc_resume()
3551 	WREG32(IH_CNTL, ih_cntl);  in r600_enable_interrupts()
3552 	WREG32(IH_RB_CNTL, ih_rb_cntl);  in r600_enable_interrupts()
3563 	WREG32(IH_RB_CNTL, ih_rb_cntl);  in r600_disable_interrupts()
3564 	WREG32(IH_CNTL, ih_cntl);  in r600_disable_interrupts()
3566 	WREG32(IH_RB_RPTR, 0);  in r600_disable_interrupts()
3567 	WREG32(IH_RB_WPTR, 0);  in r600_disable_interrupts()
3576 	WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);  in r600_disable_interrupt_state()
3578 	WREG32(DMA_CNTL, tmp);  in r600_disable_interrupt_state()
3579 	WREG32(GRBM_INT_CNTL, 0);  in r600_disable_interrupt_state()
3580 	WREG32(DxMODE_INT_MASK, 0);  in r600_disable_interrupt_state()
3581 	WREG32(D1GRPH_INTERRUPT_CONTROL, 0);  in r600_disable_interrupt_state()
3582 	WREG32(D2GRPH_INTERRUPT_CONTROL, 0);  in r600_disable_interrupt_state()
3584 		WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);  in r600_disable_interrupt_state()
3585 		WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);  in r600_disable_interrupt_state()
3587 		WREG32(DC_HPD1_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3589 		WREG32(DC_HPD2_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3591 		WREG32(DC_HPD3_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3593 		WREG32(DC_HPD4_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3596 			WREG32(DC_HPD5_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3598 			WREG32(DC_HPD6_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3600 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);  in r600_disable_interrupt_state()
3602 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);  in r600_disable_interrupt_state()
3605 			WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);  in r600_disable_interrupt_state()
3607 			WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);  in r600_disable_interrupt_state()
3610 		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);  in r600_disable_interrupt_state()
3611 		WREG32(DACB_AUTODETECT_INT_CONTROL, 0);  in r600_disable_interrupt_state()
3613 		WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3615 		WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3617 		WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);  in r600_disable_interrupt_state()
3619 		WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);  in r600_disable_interrupt_state()
3621 		WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);  in r600_disable_interrupt_state()
3651 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3659 	WREG32(INTERRUPT_CNTL, interrupt_cntl);  in r600_irq_init()
3661 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3672 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);  in r600_irq_init()
3673 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in r600_irq_init()
3675 	WREG32(IH_RB_CNTL, ih_rb_cntl);  in r600_irq_init()
3678 	WREG32(IH_RB_RPTR, 0);  in r600_irq_init()
3679 	WREG32(IH_RB_WPTR, 0);  in r600_irq_init()
3686 	WREG32(IH_CNTL, ih_cntl);  in r600_irq_init()
3827 	WREG32(CP_INT_CNTL, cp_int_cntl);  in r600_irq_set()
3828 	WREG32(DMA_CNTL, dma_cntl);  in r600_irq_set()
3829 	WREG32(DxMODE_INT_MASK, mode_int);  in r600_irq_set()
3830 	WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);  in r600_irq_set()
3831 	WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);  in r600_irq_set()
3832 	WREG32(GRBM_INT_CNTL, grbm_int_cntl);  in r600_irq_set()
3834 		WREG32(DC_HPD1_INT_CONTROL, hpd1);  in r600_irq_set()
3835 		WREG32(DC_HPD2_INT_CONTROL, hpd2);  in r600_irq_set()
3836 		WREG32(DC_HPD3_INT_CONTROL, hpd3);  in r600_irq_set()
3837 		WREG32(DC_HPD4_INT_CONTROL, hpd4);  in r600_irq_set()
3839 			WREG32(DC_HPD5_INT_CONTROL, hpd5);  in r600_irq_set()
3840 			WREG32(DC_HPD6_INT_CONTROL, hpd6);  in r600_irq_set()
3841 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);  in r600_irq_set()
3842 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);  in r600_irq_set()
3844 			WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);  in r600_irq_set()
3845 			WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);  in r600_irq_set()
3848 		WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);  in r600_irq_set()
3849 		WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);  in r600_irq_set()
3850 		WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);  in r600_irq_set()
3851 		WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);  in r600_irq_set()
3852 		WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);  in r600_irq_set()
3855 		WREG32(CG_THERMAL_INT, thermal_int);  in r600_irq_set()
3857 		WREG32(RV770_CG_THERMAL_INT, thermal_int);  in r600_irq_set()
3892 		WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);  in r600_irq_ack()
3894 		WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);  in r600_irq_ack()
3896 		WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);  in r600_irq_ack()
3898 		WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);  in r600_irq_ack()
3900 		WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);  in r600_irq_ack()
3902 		WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);  in r600_irq_ack()
3907 			WREG32(DC_HPD1_INT_CONTROL, tmp);  in r600_irq_ack()
3911 			WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);  in r600_irq_ack()
3918 			WREG32(DC_HPD2_INT_CONTROL, tmp);  in r600_irq_ack()
3922 			WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);  in r600_irq_ack()
3929 			WREG32(DC_HPD3_INT_CONTROL, tmp);  in r600_irq_ack()
3933 			WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);  in r600_irq_ack()
3939 		WREG32(DC_HPD4_INT_CONTROL, tmp);  in r600_irq_ack()
3945 			WREG32(DC_HPD5_INT_CONTROL, tmp);  in r600_irq_ack()
3950 			WREG32(DC_HPD6_INT_CONTROL, tmp);  in r600_irq_ack()
3955 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);  in r600_irq_ack()
3960 			WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);  in r600_irq_ack()
3966 			WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);  in r600_irq_ack()
3972 				WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);  in r600_irq_ack()
3976 				WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);  in r600_irq_ack()
4011 		WREG32(IH_RB_CNTL, tmp);  in r600_get_ih_wptr()
4276 		WREG32(IH_RB_RPTR, rptr);  in r600_irq_process()
4346 		WREG32(HDP_DEBUG1, 0);  in r600_mmio_hdp_flush()
4349 		WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);  in r600_mmio_hdp_flush()
4505 			WREG32(MM_CFGREGS_CNTL, 0x8);  in r600_pcie_gen2_enable()
4507 			WREG32(MM_CFGREGS_CNTL, 0);  in r600_pcie_gen2_enable()
4521 		WREG32(0x541c, tmp | 0x8);  in r600_pcie_gen2_enable()
4522 		WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);  in r600_pcie_gen2_enable()
4527 		WREG32(MM_CFGREGS_CNTL, 0);  in r600_pcie_gen2_enable()
4569 	WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);  in r600_get_gpu_clock_counter()