Lines Matching refs:rdev
39 void r420_pm_init_profile(struct radeon_device *rdev) in r420_pm_init_profile() argument
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
78 static void r420_set_reg_safe(struct radeon_device *rdev) in r420_set_reg_safe() argument
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; in r420_set_reg_safe()
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); in r420_set_reg_safe()
84 void r420_pipes_init(struct radeon_device *rdev) in r420_pipes_init() argument
94 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
103 if ((rdev->pdev->device == 0x5e4c) || in r420_pipes_init()
104 (rdev->pdev->device == 0x5e4f)) in r420_pipes_init()
107 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
130 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
143 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
148 if (rdev->family == CHIP_RV530) { in r420_pipes_init()
151 rdev->num_z_pipes = 2; in r420_pipes_init()
153 rdev->num_z_pipes = 1; in r420_pipes_init()
155 rdev->num_z_pipes = 1; in r420_pipes_init()
158 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
161 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) in r420_mc_rreg() argument
166 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
169 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
173 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r420_mc_wreg() argument
177 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
181 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
184 static void r420_debugfs(struct radeon_device *rdev) in r420_debugfs() argument
186 if (r100_debugfs_rbbm_init(rdev)) { in r420_debugfs()
189 if (r420_debugfs_pipes_info_init(rdev)) { in r420_debugfs()
194 static void r420_clock_resume(struct radeon_device *rdev) in r420_clock_resume() argument
199 radeon_atom_set_clock_gating(rdev, 1); in r420_clock_resume()
202 if (rdev->family == CHIP_R420) in r420_clock_resume()
207 static void r420_cp_errata_init(struct radeon_device *rdev) in r420_cp_errata_init() argument
209 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
217 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
218 radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_init()
220 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
222 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_init()
225 static void r420_cp_errata_fini(struct radeon_device *rdev) in r420_cp_errata_fini() argument
227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
232 radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_fini()
235 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_fini()
236 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
239 static int r420_startup(struct radeon_device *rdev) in r420_startup() argument
244 r100_set_common_regs(rdev); in r420_startup()
246 r300_mc_program(rdev); in r420_startup()
248 r420_clock_resume(rdev); in r420_startup()
251 if (rdev->flags & RADEON_IS_PCIE) { in r420_startup()
252 r = rv370_pcie_gart_enable(rdev); in r420_startup()
256 if (rdev->flags & RADEON_IS_PCI) { in r420_startup()
257 r = r100_pci_gart_enable(rdev); in r420_startup()
261 r420_pipes_init(rdev); in r420_startup()
264 r = radeon_wb_init(rdev); in r420_startup()
268 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
270 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r420_startup()
275 if (!rdev->irq.installed) { in r420_startup()
276 r = radeon_irq_kms_init(rdev); in r420_startup()
281 r100_irq_set(rdev); in r420_startup()
282 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
284 r = r100_cp_init(rdev, 1024 * 1024); in r420_startup()
286 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r420_startup()
289 r420_cp_errata_init(rdev); in r420_startup()
291 r = radeon_ib_pool_init(rdev); in r420_startup()
293 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r420_startup()
300 int r420_resume(struct radeon_device *rdev) in r420_resume() argument
305 if (rdev->flags & RADEON_IS_PCIE) in r420_resume()
306 rv370_pcie_gart_disable(rdev); in r420_resume()
307 if (rdev->flags & RADEON_IS_PCI) in r420_resume()
308 r100_pci_gart_disable(rdev); in r420_resume()
310 r420_clock_resume(rdev); in r420_resume()
312 if (radeon_asic_reset(rdev)) { in r420_resume()
313 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
318 if (rdev->is_atom_bios) { in r420_resume()
319 atom_asic_init(rdev->mode_info.atom_context); in r420_resume()
321 radeon_combios_asic_init(rdev->ddev); in r420_resume()
324 r420_clock_resume(rdev); in r420_resume()
326 radeon_surface_init(rdev); in r420_resume()
328 rdev->accel_working = true; in r420_resume()
329 r = r420_startup(rdev); in r420_resume()
331 rdev->accel_working = false; in r420_resume()
336 int r420_suspend(struct radeon_device *rdev) in r420_suspend() argument
338 radeon_pm_suspend(rdev); in r420_suspend()
339 r420_cp_errata_fini(rdev); in r420_suspend()
340 r100_cp_disable(rdev); in r420_suspend()
341 radeon_wb_disable(rdev); in r420_suspend()
342 r100_irq_disable(rdev); in r420_suspend()
343 if (rdev->flags & RADEON_IS_PCIE) in r420_suspend()
344 rv370_pcie_gart_disable(rdev); in r420_suspend()
345 if (rdev->flags & RADEON_IS_PCI) in r420_suspend()
346 r100_pci_gart_disable(rdev); in r420_suspend()
350 void r420_fini(struct radeon_device *rdev) in r420_fini() argument
352 radeon_pm_fini(rdev); in r420_fini()
353 r100_cp_fini(rdev); in r420_fini()
354 radeon_wb_fini(rdev); in r420_fini()
355 radeon_ib_pool_fini(rdev); in r420_fini()
356 radeon_gem_fini(rdev); in r420_fini()
357 if (rdev->flags & RADEON_IS_PCIE) in r420_fini()
358 rv370_pcie_gart_fini(rdev); in r420_fini()
359 if (rdev->flags & RADEON_IS_PCI) in r420_fini()
360 r100_pci_gart_fini(rdev); in r420_fini()
361 radeon_agp_fini(rdev); in r420_fini()
362 radeon_irq_kms_fini(rdev); in r420_fini()
363 radeon_fence_driver_fini(rdev); in r420_fini()
364 radeon_bo_fini(rdev); in r420_fini()
365 if (rdev->is_atom_bios) { in r420_fini()
366 radeon_atombios_fini(rdev); in r420_fini()
368 radeon_combios_fini(rdev); in r420_fini()
370 kfree(rdev->bios); in r420_fini()
371 rdev->bios = NULL; in r420_fini()
374 int r420_init(struct radeon_device *rdev) in r420_init() argument
379 radeon_scratch_init(rdev); in r420_init()
381 radeon_surface_init(rdev); in r420_init()
384 r100_restore_sanity(rdev); in r420_init()
386 if (!radeon_get_bios(rdev)) { in r420_init()
387 if (ASIC_IS_AVIVO(rdev)) in r420_init()
390 if (rdev->is_atom_bios) { in r420_init()
391 r = radeon_atombios_init(rdev); in r420_init()
396 r = radeon_combios_init(rdev); in r420_init()
402 if (radeon_asic_reset(rdev)) { in r420_init()
403 dev_warn(rdev->dev, in r420_init()
409 if (radeon_boot_test_post_card(rdev) == false) in r420_init()
413 radeon_get_clock_info(rdev->ddev); in r420_init()
415 if (rdev->flags & RADEON_IS_AGP) { in r420_init()
416 r = radeon_agp_init(rdev); in r420_init()
418 radeon_agp_disable(rdev); in r420_init()
422 r300_mc_init(rdev); in r420_init()
423 r420_debugfs(rdev); in r420_init()
425 r = radeon_fence_driver_init(rdev); in r420_init()
430 r = radeon_bo_init(rdev); in r420_init()
434 if (rdev->family == CHIP_R420) in r420_init()
435 r100_enable_bm(rdev); in r420_init()
437 if (rdev->flags & RADEON_IS_PCIE) { in r420_init()
438 r = rv370_pcie_gart_init(rdev); in r420_init()
442 if (rdev->flags & RADEON_IS_PCI) { in r420_init()
443 r = r100_pci_gart_init(rdev); in r420_init()
447 r420_set_reg_safe(rdev); in r420_init()
450 radeon_pm_init(rdev); in r420_init()
452 rdev->accel_working = true; in r420_init()
453 r = r420_startup(rdev); in r420_init()
456 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r420_init()
457 r100_cp_fini(rdev); in r420_init()
458 radeon_wb_fini(rdev); in r420_init()
459 radeon_ib_pool_fini(rdev); in r420_init()
460 radeon_irq_kms_fini(rdev); in r420_init()
461 if (rdev->flags & RADEON_IS_PCIE) in r420_init()
462 rv370_pcie_gart_fini(rdev); in r420_init()
463 if (rdev->flags & RADEON_IS_PCI) in r420_init()
464 r100_pci_gart_fini(rdev); in r420_init()
465 radeon_agp_fini(rdev); in r420_init()
466 rdev->accel_working = false; in r420_init()
479 struct radeon_device *rdev = dev->dev_private; in r420_debugfs_pipes_info() local
496 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) in r420_debugfs_pipes_info_init() argument
499 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); in r420_debugfs_pipes_info_init()