84 	uint32_t tmp;  in rv370_pcie_gart_tlb_flush()  local
89 		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_tlb_flush()
90 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);  in rv370_pcie_gart_tlb_flush()
92 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_tlb_flush()
150 	uint32_t tmp;  in rv370_pcie_gart_enable()  local
161 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_enable()
162 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
164 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;  in rv370_pcie_gart_enable()
165 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);  in rv370_pcie_gart_enable()
175 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_enable()
176 	tmp |= RADEON_PCIE_TX_GART_EN;  in rv370_pcie_gart_enable()
177 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_enable()
178 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
189 	u32 tmp;  in rv370_pcie_gart_disable()  local
195 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_disable()
196 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_disable()
197 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);  in rv370_pcie_gart_disable()
345 	uint32_t tmp;  in r300_mc_wait_for_idle()  local
349 		tmp = RREG32(RADEON_MC_STATUS);  in r300_mc_wait_for_idle()
350 		if (tmp & R300_MC_IDLE) {  in r300_mc_wait_for_idle()
360 	uint32_t gb_tile_config, tmp;  in r300_gpu_init()  local
394 	tmp = RREG32(R300_DST_PIPE_CONFIG);  in r300_gpu_init()
395 	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);  in r300_gpu_init()
416 	u32 status, tmp;  in r300_asic_reset()  local
428 	tmp = RREG32(RADEON_CP_RB_CNTL);  in r300_asic_reset()
429 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);  in r300_asic_reset()
432 	WREG32(RADEON_CP_RB_CNTL, tmp);  in r300_asic_reset()
476 	u32 tmp;  in r300_mc_init()  local
480 	tmp = RREG32(RADEON_MEM_CNTL);  in r300_mc_init()
481 	tmp &= R300_MEM_NUM_CHANNELS_MASK;  in r300_mc_init()
482 	switch (tmp) {  in r300_mc_init()
595 	uint32_t tmp;  in rv370_debugfs_pcie_gart_info()  local
597 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_debugfs_pcie_gart_info()
598 	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
599 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);  in rv370_debugfs_pcie_gart_info()
600 	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
601 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);  in rv370_debugfs_pcie_gart_info()
602 	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
603 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);  in rv370_debugfs_pcie_gart_info()
604 	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
605 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);  in rv370_debugfs_pcie_gart_info()
606 	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
607 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);  in rv370_debugfs_pcie_gart_info()
608 	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
609 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);  in rv370_debugfs_pcie_gart_info()
610 	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
635 	uint32_t tmp, tile_flags = 0;  in r300_packet0_check()  local
727 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
728 			tmp |= tile_flags;  in r300_packet0_check()
729 			ib[idx] = tmp;  in r300_packet0_check()
796 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
797 			tmp |= tile_flags;  in r300_packet0_check()
798 			ib[idx] = tmp;  in r300_packet0_check()
881 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
882 			tmp |= tile_flags;  in r300_packet0_check()
883 			ib[idx] = tmp;  in r300_packet0_check()
916 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
917 		track->textures[i].tex_coord_type = tmp;  in r300_packet0_check()
1002 		tmp = idx_value & 0x7;  in r300_packet0_check()
1003 		if (tmp == 2 || tmp == 4 || tmp == 6) {  in r300_packet0_check()
1006 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1007 		if (tmp == 2 || tmp == 4 || tmp == 6) {  in r300_packet0_check()
1030 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1031 		track->textures[i].pitch = tmp + 1;  in r300_packet0_check()
1033 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1034 			track->textures[i].width_11 = tmp;  in r300_packet0_check()
1035 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1036 			track->textures[i].height_11 = tmp;  in r300_packet0_check()
1068 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1069 		track->textures[i].width = tmp + 1;  in r300_packet0_check()
1070 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1071 		track->textures[i].height = tmp + 1;  in r300_packet0_check()
1072 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1073 		track->textures[i].num_levels = tmp;  in r300_packet0_check()
1074 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1075 		track->textures[i].use_pitch = !!tmp;  in r300_packet0_check()
1076 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1077 		track->textures[i].txdepth = tmp;  in r300_packet0_check()
1363 	u32 tmp;  in r300_clock_startup()  local
1368 	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);  in r300_clock_startup()
1369 	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);  in r300_clock_startup()
1371 		tmp |= S_00000D_FORCE_VAP(1);  in r300_clock_startup()
1372 	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);  in r300_clock_startup()