632 	struct radeon_bo_list *reloc;  in r300_packet0_check()  local
666 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
673 		track->cb[i].robj = reloc->robj;  in r300_packet0_check()
676 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
679 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
686 		track->zb.robj = reloc->robj;  in r300_packet0_check()
689 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
708 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
718 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
720 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
722 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
724 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
727 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
731 		track->textures[i].robj = reloc->robj;  in r300_packet0_check()
781 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
789 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
791 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
793 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
866 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
874 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
876 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
878 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
1081 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1088 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1123 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1130 		track->aa.robj = reloc->robj;  in r300_packet0_check()
1133 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1176 	struct radeon_bo_list *reloc;  in r300_packet3_check()  local
1192 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1198 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r300_packet3_check()
1199 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r300_packet3_check()