Lines Matching refs:WREG32
61 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_rreg()
72 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_wreg()
73 WREG32(RADEON_PCIE_DATA, (v)); in rv370_pcie_wreg()
387 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); in r300_gpu_init()
395 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); in r300_gpu_init()
397 WREG32(R300_RB2D_DSTCACHE_MODE, in r300_gpu_init()
427 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
430 WREG32(RADEON_CP_RB_RPTR_WR, 0); in r300_asic_reset()
431 WREG32(RADEON_CP_RB_WPTR, 0); in r300_asic_reset()
432 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | in r300_asic_reset()
441 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); in r300_asic_reset()
450 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); in r300_asic_reset()
453 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); in r300_asic_reset()
1340 WREG32(R_00014C_MC_AGP_LOCATION, in r300_mc_program()
1343 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r300_mc_program()
1344 WREG32(R_00015C_AGP_BASE_2, in r300_mc_program()
1347 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); in r300_mc_program()
1348 WREG32(R_000170_AGP_BASE, 0); in r300_mc_program()
1349 WREG32(R_00015C_AGP_BASE_2, 0); in r300_mc_program()
1355 WREG32(R_000148_MC_FB_LOCATION, in r300_mc_program()