157 	u32 idx_value;  in r200_packet0_check()  local
161 	idx_value = radeon_get_ib_value(p, idx);  in r200_packet0_check()
189 		track->zb.offset = idx_value;  in r200_packet0_check()
191 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r200_packet0_check()
202 		track->cb[0].offset = idx_value;  in r200_packet0_check()
204 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r200_packet0_check()
226 			tmp = idx_value & ~(0x7 << 2);  in r200_packet0_check()
230 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r200_packet0_check()
273 		track->textures[i].cube_info[face - 1].offset = idx_value;  in r200_packet0_check()
274 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r200_packet0_check()
279 		track->maxy = ((idx_value >> 16) & 0x7FF);  in r200_packet0_check()
298 			tmp = idx_value & ~(0x7 << 16);  in r200_packet0_check()
302 			ib[idx] = idx_value;  in r200_packet0_check()
304 		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;  in r200_packet0_check()
308 		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;  in r200_packet0_check()
312 		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {  in r200_packet0_check()
330 				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));  in r200_packet0_check()
333 		if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {  in r200_packet0_check()
338 		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);  in r200_packet0_check()
343 		switch (idx_value & 0xf) {  in r200_packet0_check()
368 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r200_packet0_check()
372 			uint32_t temp = idx_value >> 4;  in r200_packet0_check()
379 		track->vap_vf_cntl = idx_value;  in r200_packet0_check()
383 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r200_packet0_check()
386 		track->vtx_size = r200_get_vtx_size_0(idx_value);  in r200_packet0_check()
389 		track->vtx_size += r200_get_vtx_size_1(idx_value);  in r200_packet0_check()
398 		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;  in r200_packet0_check()
399 		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;  in r200_packet0_check()
409 		track->textures[i].pitch = idx_value + 32;  in r200_packet0_check()
419 		track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)  in r200_packet0_check()
421 		tmp = (idx_value >> 23) & 0x7;  in r200_packet0_check()
424 		tmp = (idx_value >> 27) & 0x7;  in r200_packet0_check()
444 		track->textures[i].txdepth = idx_value & 0x7;  in r200_packet0_check()
445 		tmp = (idx_value >> 16) & 0x3;  in r200_packet0_check()
475 		if (idx_value & R200_TXFORMAT_NON_POWER2) {  in r200_packet0_check()
479 …track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDT…  in r200_packet0_check()
480 …track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HE…  in r200_packet0_check()
482 		if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)  in r200_packet0_check()
484 		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {  in r200_packet0_check()
521 		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);  in r200_packet0_check()
522 		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);  in r200_packet0_check()
531 		tmp = idx_value;  in r200_packet0_check()