Lines Matching refs:table
990 struct radeon_clock_voltage_dependency_table *table) in ni_patch_single_dependency_table_based_on_leakage() argument
995 if (table) { in ni_patch_single_dependency_table_based_on_leakage()
996 for (i = 0; i < table->count; i++) { in ni_patch_single_dependency_table_based_on_leakage()
997 if (0xff01 == table->entries[i].v) { in ni_patch_single_dependency_table_based_on_leakage()
1000 table->entries[i].v = pi->max_vddc; in ni_patch_single_dependency_table_based_on_leakage()
1259 NISLANDS_SMC_STATETABLE *table) in ni_populate_smc_voltage_table() argument
1264 table->highSMIO[i] = 0; in ni_populate_smc_voltage_table()
1265 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); in ni_populate_smc_voltage_table()
1270 NISLANDS_SMC_STATETABLE *table) in ni_populate_smc_voltage_tables() argument
1277 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); in ni_populate_smc_voltage_tables()
1278 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0; in ni_populate_smc_voltage_tables()
1279 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = in ni_populate_smc_voltage_tables()
1284 table->maxVDDCIndexInPPTable = i; in ni_populate_smc_voltage_tables()
1291 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); in ni_populate_smc_voltage_tables()
1293 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0; in ni_populate_smc_voltage_tables()
1294 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = in ni_populate_smc_voltage_tables()
1300 struct atom_voltage_table *table, in ni_populate_voltage_value() argument
1306 for (i = 0; i < table->count; i++) { in ni_populate_voltage_value()
1307 if (value <= table->entries[i].value) { in ni_populate_voltage_value()
1309 voltage->value = cpu_to_be16(table->entries[i].value); in ni_populate_voltage_value()
1314 if (i >= table->count) in ni_populate_voltage_value()
1683 NISLANDS_SMC_STATETABLE *table) in ni_populate_smc_initial_state() argument
1692 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in ni_populate_smc_initial_state()
1694 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1696 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in ni_populate_smc_initial_state()
1698 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1700 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in ni_populate_smc_initial_state()
1702 table->initialState.levels[0].mclk.vDLL_CNTL = in ni_populate_smc_initial_state()
1704 table->initialState.levels[0].mclk.vMPLL_SS = in ni_populate_smc_initial_state()
1706 table->initialState.levels[0].mclk.vMPLL_SS2 = in ni_populate_smc_initial_state()
1708 table->initialState.levels[0].mclk.mclk_value = in ni_populate_smc_initial_state()
1711 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in ni_populate_smc_initial_state()
1713 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1715 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in ni_populate_smc_initial_state()
1717 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = in ni_populate_smc_initial_state()
1719 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = in ni_populate_smc_initial_state()
1721 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in ni_populate_smc_initial_state()
1723 table->initialState.levels[0].sclk.sclk_value = in ni_populate_smc_initial_state()
1725 table->initialState.levels[0].arbRefreshState = in ni_populate_smc_initial_state()
1728 table->initialState.levels[0].ACIndex = 0; in ni_populate_smc_initial_state()
1732 &table->initialState.levels[0].vddc); in ni_populate_smc_initial_state()
1737 &table->initialState.levels[0].vddc, in ni_populate_smc_initial_state()
1741 table->initialState.levels[0].vddc.index, in ni_populate_smc_initial_state()
1742 &table->initialState.levels[0].std_vddc); in ni_populate_smc_initial_state()
1749 &table->initialState.levels[0].vddci); in ni_populate_smc_initial_state()
1751 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); in ni_populate_smc_initial_state()
1754 table->initialState.levels[0].aT = cpu_to_be32(reg); in ni_populate_smc_initial_state()
1756 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); in ni_populate_smc_initial_state()
1759 table->initialState.levels[0].gen2PCIE = 1; in ni_populate_smc_initial_state()
1761 table->initialState.levels[0].gen2PCIE = 0; in ni_populate_smc_initial_state()
1764 table->initialState.levels[0].strobeMode = in ni_populate_smc_initial_state()
1769 … table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG; in ni_populate_smc_initial_state()
1771 table->initialState.levels[0].mcFlags = 0; in ni_populate_smc_initial_state()
1774 table->initialState.levelCount = 1; in ni_populate_smc_initial_state()
1776 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; in ni_populate_smc_initial_state()
1778 table->initialState.levels[0].dpm2.MaxPS = 0; in ni_populate_smc_initial_state()
1779 table->initialState.levels[0].dpm2.NearTDPDec = 0; in ni_populate_smc_initial_state()
1780 table->initialState.levels[0].dpm2.AboveSafeInc = 0; in ni_populate_smc_initial_state()
1781 table->initialState.levels[0].dpm2.BelowSafeInc = 0; in ni_populate_smc_initial_state()
1784 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); in ni_populate_smc_initial_state()
1787 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); in ni_populate_smc_initial_state()
1793 NISLANDS_SMC_STATETABLE *table) in ni_populate_smc_acpi_state() argument
1811 table->ACPIState = table->initialState; in ni_populate_smc_acpi_state()
1813 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; in ni_populate_smc_acpi_state()
1818 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); in ni_populate_smc_acpi_state()
1823 &table->ACPIState.levels[0].vddc, &std_vddc); in ni_populate_smc_acpi_state()
1826 table->ACPIState.levels[0].vddc.index, in ni_populate_smc_acpi_state()
1827 &table->ACPIState.levels[0].std_vddc); in ni_populate_smc_acpi_state()
1832 table->ACPIState.levels[0].gen2PCIE = 1; in ni_populate_smc_acpi_state()
1834 table->ACPIState.levels[0].gen2PCIE = 0; in ni_populate_smc_acpi_state()
1836 table->ACPIState.levels[0].gen2PCIE = 0; in ni_populate_smc_acpi_state()
1842 &table->ACPIState.levels[0].vddc); in ni_populate_smc_acpi_state()
1847 &table->ACPIState.levels[0].vddc, in ni_populate_smc_acpi_state()
1851 table->ACPIState.levels[0].vddc.index, in ni_populate_smc_acpi_state()
1852 &table->ACPIState.levels[0].std_vddc); in ni_populate_smc_acpi_state()
1854 table->ACPIState.levels[0].gen2PCIE = 0; in ni_populate_smc_acpi_state()
1862 &table->ACPIState.levels[0].vddci); in ni_populate_smc_acpi_state()
1905 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in ni_populate_smc_acpi_state()
1906 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in ni_populate_smc_acpi_state()
1907 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in ni_populate_smc_acpi_state()
1908 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in ni_populate_smc_acpi_state()
1909 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in ni_populate_smc_acpi_state()
1910 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl); in ni_populate_smc_acpi_state()
1912 table->ACPIState.levels[0].mclk.mclk_value = 0; in ni_populate_smc_acpi_state()
1914 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in ni_populate_smc_acpi_state()
1915 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in ni_populate_smc_acpi_state()
1916 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in ni_populate_smc_acpi_state()
1917 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4); in ni_populate_smc_acpi_state()
1919 table->ACPIState.levels[0].sclk.sclk_value = 0; in ni_populate_smc_acpi_state()
1921 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); in ni_populate_smc_acpi_state()
1924 table->ACPIState.levels[0].ACIndex = 1; in ni_populate_smc_acpi_state()
1926 table->ACPIState.levels[0].dpm2.MaxPS = 0; in ni_populate_smc_acpi_state()
1927 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; in ni_populate_smc_acpi_state()
1928 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; in ni_populate_smc_acpi_state()
1929 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; in ni_populate_smc_acpi_state()
1932 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); in ni_populate_smc_acpi_state()
1935 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); in ni_populate_smc_acpi_state()
1946 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable; in ni_init_smc_table() local
1948 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE)); in ni_init_smc_table()
1950 ni_populate_smc_voltage_tables(rdev, table); in ni_init_smc_table()
1955 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; in ni_init_smc_table()
1958 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; in ni_init_smc_table()
1961 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; in ni_init_smc_table()
1966 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ni_init_smc_table()
1969 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; in ni_init_smc_table()
1972 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ni_init_smc_table()
1975 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ni_init_smc_table()
1977 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table); in ni_init_smc_table()
1981 ret = ni_populate_smc_acpi_state(rdev, table); in ni_init_smc_table()
1985 table->driverState = table->initialState; in ni_init_smc_table()
1987 table->ULVState = table->initialState; in ni_init_smc_table()
1994 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table, in ni_init_smc_table()
2710 struct ni_mc_reg_table *table) in ni_set_mc_special_registers() argument
2716 for (i = 0, j = table->last; i < table->last; i++) { in ni_set_mc_special_registers()
2717 switch (table->mc_reg_address[i].s1) { in ni_set_mc_special_registers()
2722 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ni_set_mc_special_registers()
2723 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ni_set_mc_special_registers()
2724 for (k = 0; k < table->num_entries; k++) in ni_set_mc_special_registers()
2725 table->mc_reg_table_entry[k].mc_data[j] = in ni_set_mc_special_registers()
2727 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ni_set_mc_special_registers()
2733 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ni_set_mc_special_registers()
2734 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ni_set_mc_special_registers()
2735 for(k = 0; k < table->num_entries; k++) { in ni_set_mc_special_registers()
2736 table->mc_reg_table_entry[k].mc_data[j] = in ni_set_mc_special_registers()
2738 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ni_set_mc_special_registers()
2740 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ni_set_mc_special_registers()
2748 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ni_set_mc_special_registers()
2749 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ni_set_mc_special_registers()
2750 for (k = 0; k < table->num_entries; k++) in ni_set_mc_special_registers()
2751 table->mc_reg_table_entry[k].mc_data[j] = in ni_set_mc_special_registers()
2753 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ni_set_mc_special_registers()
2763 table->last = j; in ni_set_mc_special_registers()
2820 static void ni_set_valid_flag(struct ni_mc_reg_table *table) in ni_set_valid_flag() argument
2824 for (i = 0; i < table->last; i++) { in ni_set_valid_flag()
2825 for (j = 1; j < table->num_entries; j++) { in ni_set_valid_flag()
2826 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { in ni_set_valid_flag()
2827 table->valid_flag |= 1 << i; in ni_set_valid_flag()
2834 static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table) in ni_set_s0_mc_reg_index() argument
2839 for (i = 0; i < table->last; i++) in ni_set_s0_mc_reg_index()
2840 table->mc_reg_address[i].s0 = in ni_set_s0_mc_reg_index()
2841 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ni_set_s0_mc_reg_index()
2842 address : table->mc_reg_address[i].s1; in ni_set_s0_mc_reg_index()
2845 static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, in ni_copy_vbios_mc_reg_table() argument
2850 if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) in ni_copy_vbios_mc_reg_table()
2852 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ni_copy_vbios_mc_reg_table()
2855 for (i = 0; i < table->last; i++) in ni_copy_vbios_mc_reg_table()
2856 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ni_copy_vbios_mc_reg_table()
2857 ni_table->last = table->last; in ni_copy_vbios_mc_reg_table()
2859 for (i = 0; i < table->num_entries; i++) { in ni_copy_vbios_mc_reg_table()
2861 table->mc_reg_table_entry[i].mclk_max; in ni_copy_vbios_mc_reg_table()
2862 for (j = 0; j < table->last; j++) in ni_copy_vbios_mc_reg_table()
2864 table->mc_reg_table_entry[i].mc_data[j]; in ni_copy_vbios_mc_reg_table()
2866 ni_table->num_entries = table->num_entries; in ni_copy_vbios_mc_reg_table()
2875 struct atom_mc_reg_table *table; in ni_initialize_mc_reg_table() local
2879 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ni_initialize_mc_reg_table()
2880 if (!table) in ni_initialize_mc_reg_table()
2897 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ni_initialize_mc_reg_table()
2902 ret = ni_copy_vbios_mc_reg_table(table, ni_table); in ni_initialize_mc_reg_table()
2917 kfree(table); in ni_initialize_mc_reg_table()