721 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
722 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
724 extern int ni_mc_load_microcode(struct radeon_device *rdev);
726 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)  in ni_get_pi()  argument
728         struct ni_power_info *pi = rdev->pm.dpm.priv;  in ni_get_pi()
761 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,  in ni_calculate_leakage_for_v_and_t()  argument
771 bool ni_dpm_vblank_too_short(struct radeon_device *rdev)  in ni_dpm_vblank_too_short()  argument
773 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_dpm_vblank_too_short()
774 	u32 vblank_time = r600_dpm_get_vblank_time(rdev);  in ni_dpm_vblank_too_short()
785 static void ni_apply_state_adjust_rules(struct radeon_device *rdev,  in ni_apply_state_adjust_rules()  argument
795 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in ni_apply_state_adjust_rules()
796 	    ni_dpm_vblank_too_short(rdev))  in ni_apply_state_adjust_rules()
801 	if (rdev->pm.dpm.ac_power)  in ni_apply_state_adjust_rules()
802 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_apply_state_adjust_rules()
804 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ni_apply_state_adjust_rules()
806 	if (rdev->pm.dpm.ac_power == false) {  in ni_apply_state_adjust_rules()
829 	btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,  in ni_apply_state_adjust_rules()
864 		btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,  in ni_apply_state_adjust_rules()
869 		btc_adjust_clock_combinations(rdev, max_limits,  in ni_apply_state_adjust_rules()
873 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in ni_apply_state_adjust_rules()
876 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in ni_apply_state_adjust_rules()
879 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in ni_apply_state_adjust_rules()
882 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in ni_apply_state_adjust_rules()
883 						   rdev->clock.current_dispclk,  in ni_apply_state_adjust_rules()
888 		btc_apply_voltage_delta_rules(rdev,  in ni_apply_state_adjust_rules()
896 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in ni_apply_state_adjust_rules()
899 		if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)  in ni_apply_state_adjust_rules()
904 static void ni_cg_clockgating_default(struct radeon_device *rdev)  in ni_cg_clockgating_default()  argument
912 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_cg_clockgating_default()
915 static void ni_gfx_clockgating_enable(struct radeon_device *rdev,  in ni_gfx_clockgating_enable()  argument
929 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_gfx_clockgating_enable()
932 static void ni_mg_clockgating_default(struct radeon_device *rdev)  in ni_mg_clockgating_default()  argument
940 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_mg_clockgating_default()
943 static void ni_mg_clockgating_enable(struct radeon_device *rdev,  in ni_mg_clockgating_enable()  argument
957 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_mg_clockgating_enable()
960 static void ni_ls_clockgating_default(struct radeon_device *rdev)  in ni_ls_clockgating_default()  argument
968 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_ls_clockgating_default()
971 static void ni_ls_clockgating_enable(struct radeon_device *rdev,  in ni_ls_clockgating_enable()  argument
985 	btc_program_mgcg_hw_sequence(rdev, ps, count);  in ni_ls_clockgating_enable()
989 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,  in ni_patch_single_dependency_table_based_on_leakage()  argument
992 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_patch_single_dependency_table_based_on_leakage()
1007 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)  in ni_patch_dependency_tables_based_on_leakage()  argument
1011 	ret = ni_patch_single_dependency_table_based_on_leakage(rdev,  in ni_patch_dependency_tables_based_on_leakage()
1012 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in ni_patch_dependency_tables_based_on_leakage()
1014 	ret = ni_patch_single_dependency_table_based_on_leakage(rdev,  in ni_patch_dependency_tables_based_on_leakage()
1015 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in ni_patch_dependency_tables_based_on_leakage()
1019 static void ni_stop_dpm(struct radeon_device *rdev)  in ni_stop_dpm()  argument
1025 static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1029 		return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1036 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,  in ni_send_msg_to_smc_with_parameter()  argument
1040 	return rv770_send_msg_to_smc(rdev, msg);  in ni_send_msg_to_smc_with_parameter()
1043 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)  in ni_restrict_performance_levels_before_switch()  argument
1045 	if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)  in ni_restrict_performance_levels_before_switch()
1048 …return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK)…  in ni_restrict_performance_levels_before_switch()
1052 int ni_dpm_force_performance_level(struct radeon_device *rdev,  in ni_dpm_force_performance_level()  argument
1056 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1059 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1062 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1065 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1068 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1071 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)  in ni_dpm_force_performance_level()
1075 	rdev->pm.dpm.forced_level = level;  in ni_dpm_force_performance_level()
1080 static void ni_stop_smc(struct radeon_device *rdev)  in ni_stop_smc()  argument
1085 	for (i = 0; i < rdev->usec_timeout; i++) {  in ni_stop_smc()
1094 	r7xx_stop_smc(rdev);  in ni_stop_smc()
1097 static int ni_process_firmware_header(struct radeon_device *rdev)  in ni_process_firmware_header()  argument
1099         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_process_firmware_header()
1100         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_process_firmware_header()
1101         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_process_firmware_header()
1105 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1115 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1125 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1135 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1145 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1155 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1165 	ret = rv770_read_smc_sram_dword(rdev,  in ni_process_firmware_header()
1179 static void ni_read_clock_registers(struct radeon_device *rdev)  in ni_read_clock_registers()  argument
1181 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_read_clock_registers()
1200 static int ni_enter_ulp_state(struct radeon_device *rdev)
1202 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1220 static void ni_program_response_times(struct radeon_device *rdev)  in ni_program_response_times()  argument
1226 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);  in ni_program_response_times()
1228 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in ni_program_response_times()
1229 	backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;  in ni_program_response_times()
1240 	reference_clock = radeon_get_xclk(rdev);  in ni_program_response_times()
1249 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);  in ni_program_response_times()
1250 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);  in ni_program_response_times()
1251 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);  in ni_program_response_times()
1252 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);  in ni_program_response_times()
1253 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);  in ni_program_response_times()
1254 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);  in ni_program_response_times()
1257 static void ni_populate_smc_voltage_table(struct radeon_device *rdev,  in ni_populate_smc_voltage_table()  argument
1269 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,  in ni_populate_smc_voltage_tables()  argument
1272 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_voltage_tables()
1273 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_smc_voltage_tables()
1277 		ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);  in ni_populate_smc_voltage_tables()
1291 		ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);  in ni_populate_smc_voltage_tables()
1299 static int ni_populate_voltage_value(struct radeon_device *rdev,  in ni_populate_voltage_value()  argument
1320 static void ni_populate_mvdd_value(struct radeon_device *rdev,  in ni_populate_mvdd_value()  argument
1324         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_mvdd_value()
1325 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_mvdd_value()
1342 static int ni_get_std_voltage_value(struct radeon_device *rdev,  in ni_get_std_voltage_value()  argument
1346 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&  in ni_get_std_voltage_value()
1347 	    ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))  in ni_get_std_voltage_value()
1348 		*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in ni_get_std_voltage_value()
1355 static void ni_populate_std_voltage_value(struct radeon_device *rdev,  in ni_populate_std_voltage_value()  argument
1363 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)  in ni_get_smc_power_scaling_factor()  argument
1366 	u32 xclk = radeon_get_xclk(rdev);  in ni_get_smc_power_scaling_factor()
1380 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,  in ni_calculate_power_boost_limit()  argument
1385 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_calculate_power_boost_limit()
1386 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_calculate_power_boost_limit()
1400 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_calculate_power_boost_limit()
1406 		ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);  in ni_calculate_power_boost_limit()
1410 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_calculate_power_boost_limit()
1416 		ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);  in ni_calculate_power_boost_limit()
1432 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,  in ni_calculate_adjusted_tdp_limits()  argument
1438 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in ni_calculate_adjusted_tdp_limits()
1442 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1443 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1445 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1446 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1452 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,  in ni_populate_smc_tdp_limits()  argument
1455 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_tdp_limits()
1456 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_smc_tdp_limits()
1460 		u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);  in ni_populate_smc_tdp_limits()
1471 		ret = ni_calculate_adjusted_tdp_limits(rdev,  in ni_populate_smc_tdp_limits()
1473 						       rdev->pm.dpm.tdp_adjustment,  in ni_populate_smc_tdp_limits()
1479 		power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,  in ni_populate_smc_tdp_limits()
1492 		ret = rv770_copy_bytes_to_smc(rdev,  in ni_populate_smc_tdp_limits()
1504 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,  in ni_copy_and_switch_arb_sets()  argument
1569 static int ni_init_arb_table_index(struct radeon_device *rdev)  in ni_init_arb_table_index()  argument
1571 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_init_arb_table_index()
1572 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_init_arb_table_index()
1576 	ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_init_arb_table_index()
1584 	return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_init_arb_table_index()
1588 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)  in ni_initial_switch_from_arb_f0_to_f1()  argument
1590 	return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);  in ni_initial_switch_from_arb_f0_to_f1()
1593 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)  in ni_force_switch_to_arb_f0()  argument
1595 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_force_switch_to_arb_f0()
1596 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_force_switch_to_arb_f0()
1600 	ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_force_switch_to_arb_f0()
1610 	return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);  in ni_force_switch_to_arb_f0()
1613 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,  in ni_populate_memory_timing_parameters()  argument
1621 		(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);  in ni_populate_memory_timing_parameters()
1624 	radeon_atom_set_engine_dram_timings(rdev,  in ni_populate_memory_timing_parameters()
1637 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,  in ni_do_program_memory_timing_parameters()  argument
1641 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_do_program_memory_timing_parameters()
1642 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_do_program_memory_timing_parameters()
1648 		ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);  in ni_do_program_memory_timing_parameters()
1652 		ret = rv770_copy_bytes_to_smc(rdev,  in ni_do_program_memory_timing_parameters()
1665 static int ni_program_memory_timing_parameters(struct radeon_device *rdev,  in ni_program_memory_timing_parameters()  argument
1668 	return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,  in ni_program_memory_timing_parameters()
1672 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,  in ni_populate_initial_mvdd_value()  argument
1675 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_initial_mvdd_value()
1681 static int ni_populate_smc_initial_state(struct radeon_device *rdev,  in ni_populate_smc_initial_state()  argument
1686 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_initial_state()
1687 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_smc_initial_state()
1688 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_smc_initial_state()
1730 	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_populate_smc_initial_state()
1736 		ret = ni_get_std_voltage_value(rdev,  in ni_populate_smc_initial_state()
1740 			ni_populate_std_voltage_value(rdev, std_vddc,  in ni_populate_smc_initial_state()
1746 		ni_populate_voltage_value(rdev,  in ni_populate_smc_initial_state()
1751 	ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);  in ni_populate_smc_initial_state()
1765 			cypress_get_strobe_mode_settings(rdev,  in ni_populate_smc_initial_state()
1792 static int ni_populate_smc_acpi_state(struct radeon_device *rdev,  in ni_populate_smc_acpi_state()  argument
1795 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_acpi_state()
1796 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_smc_acpi_state()
1797 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_smc_acpi_state()
1816 		ret = ni_populate_voltage_value(rdev,  in ni_populate_smc_acpi_state()
1822 			ret = ni_get_std_voltage_value(rdev,  in ni_populate_smc_acpi_state()
1825 				ni_populate_std_voltage_value(rdev, std_vddc,  in ni_populate_smc_acpi_state()
1839 		ret = ni_populate_voltage_value(rdev,  in ni_populate_smc_acpi_state()
1846 			ret = ni_get_std_voltage_value(rdev,  in ni_populate_smc_acpi_state()
1850 				ni_populate_std_voltage_value(rdev, std_vddc,  in ni_populate_smc_acpi_state()
1859 			ni_populate_voltage_value(rdev,  in ni_populate_smc_acpi_state()
1921 	ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);  in ni_populate_smc_acpi_state()
1940 static int ni_init_smc_table(struct radeon_device *rdev)  in ni_init_smc_table()  argument
1942 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_init_smc_table()
1943 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_init_smc_table()
1945 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in ni_init_smc_table()
1950 	ni_populate_smc_voltage_tables(rdev, table);  in ni_init_smc_table()
1952 	switch (rdev->pm.int_thermal_type) {  in ni_init_smc_table()
1965 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in ni_init_smc_table()
1968 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)  in ni_init_smc_table()
1971 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in ni_init_smc_table()
1977 	ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);  in ni_init_smc_table()
1981 	ret = ni_populate_smc_acpi_state(rdev, table);  in ni_init_smc_table()
1989 	ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,  in ni_init_smc_table()
1994 	return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,  in ni_init_smc_table()
1998 static int ni_calculate_sclk_params(struct radeon_device *rdev,  in ni_calculate_sclk_params()  argument
2002 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_calculate_sclk_params()
2003 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_calculate_sclk_params()
2012 	u32 reference_clock = rdev->clock.spll.reference_freq;  in ni_calculate_sclk_params()
2017 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,  in ni_calculate_sclk_params()
2044 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,  in ni_calculate_sclk_params()
2069 static int ni_populate_sclk_value(struct radeon_device *rdev,  in ni_populate_sclk_value()  argument
2076 	ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);  in ni_populate_sclk_value()
2090 static int ni_init_smc_spll_table(struct radeon_device *rdev)  in ni_init_smc_spll_table()  argument
2092         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_init_smc_spll_table()
2093 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_init_smc_spll_table()
2112 		ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);  in ni_init_smc_spll_table()
2152 		ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,  in ni_init_smc_spll_table()
2160 static int ni_populate_mclk_value(struct radeon_device *rdev,  in ni_populate_mclk_value()  argument
2167 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_mclk_value()
2168 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_mclk_value()
2183 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,  in ni_populate_mclk_value()
2195 	ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);  in ni_populate_mclk_value()
2240 		if (radeon_atombios_get_asic_ss_info(rdev, &ss,  in ni_populate_mclk_value()
2242 			u32 reference_clock = rdev->clock.mpll.reference_freq;  in ni_populate_mclk_value()
2294 static void ni_populate_smc_sp(struct radeon_device *rdev,  in ni_populate_smc_sp()  argument
2299 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_sp()
2309 static int ni_convert_power_level_to_smc(struct radeon_device *rdev,  in ni_convert_power_level_to_smc()  argument
2313 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_convert_power_level_to_smc()
2314         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_convert_power_level_to_smc()
2315         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_convert_power_level_to_smc()
2324 	ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in ni_convert_power_level_to_smc()
2342 		level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);  in ni_convert_power_level_to_smc()
2345 			if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=  in ni_convert_power_level_to_smc()
2356 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,  in ni_convert_power_level_to_smc()
2361 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);  in ni_convert_power_level_to_smc()
2366 	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_convert_power_level_to_smc()
2371 	ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);  in ni_convert_power_level_to_smc()
2375 	ni_populate_std_voltage_value(rdev, std_vddc,  in ni_convert_power_level_to_smc()
2379 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,  in ni_convert_power_level_to_smc()
2385 	ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);  in ni_convert_power_level_to_smc()
2390 static int ni_populate_smc_t(struct radeon_device *rdev,  in ni_populate_smc_t()  argument
2394         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_smc_t()
2395         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_smc_t()
2450 static int ni_populate_power_containment_values(struct radeon_device *rdev,  in ni_populate_power_containment_values()  argument
2454         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_power_containment_values()
2455         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_power_containment_values()
2456 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_power_containment_values()
2476 	ret = ni_calculate_adjusted_tdp_limits(rdev,  in ni_populate_power_containment_values()
2478 					       rdev->pm.dpm.tdp_adjustment,  in ni_populate_power_containment_values()
2484 	power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);  in ni_populate_power_containment_values()
2486 	ret = rv770_write_smc_sram_dword(rdev,  in ni_populate_power_containment_values()
2490 					 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),  in ni_populate_power_containment_values()
2536 static int ni_populate_sq_ramping_values(struct radeon_device *rdev,  in ni_populate_sq_ramping_values()  argument
2540 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_sq_ramping_values()
2553 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in ni_populate_sq_ramping_values()
2575 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in ni_populate_sq_ramping_values()
2594 static int ni_enable_power_containment(struct radeon_device *rdev,  in ni_enable_power_containment()  argument
2598         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_enable_power_containment()
2605 				smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);  in ni_enable_power_containment()
2614 			smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);  in ni_enable_power_containment()
2624 static int ni_convert_power_state_to_smc(struct radeon_device *rdev,  in ni_convert_power_state_to_smc()  argument
2628         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_convert_power_state_to_smc()
2629 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_convert_power_state_to_smc()
2643 		ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],  in ni_convert_power_state_to_smc()
2667 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,  in ni_convert_power_state_to_smc()
2670 	ni_populate_smc_sp(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2672 	ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2676 	ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2680 	return ni_populate_smc_t(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2683 static int ni_upload_sw_state(struct radeon_device *rdev,  in ni_upload_sw_state()  argument
2686 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_upload_sw_state()
2697 	ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);  in ni_upload_sw_state()
2701 	ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);  in ni_upload_sw_state()
2709 static int ni_set_mc_special_registers(struct radeon_device *rdev,  in ni_set_mc_special_registers()  argument
2712 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_set_mc_special_registers()
2871 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)  in ni_initialize_mc_reg_table()  argument
2873 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_initialize_mc_reg_table()
2877 	u8 module_index = rv770_get_memory_module_index(rdev);  in ni_initialize_mc_reg_table()
2897 	ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);  in ni_initialize_mc_reg_table()
2909 	ret = ni_set_mc_special_registers(rdev, ni_table);  in ni_initialize_mc_reg_table()
2922 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,  in ni_populate_mc_reg_addresses()  argument
2925 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_mc_reg_addresses()
2957 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,  in ni_convert_mc_reg_table_entry_to_smc()  argument
2961 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_convert_mc_reg_table_entry_to_smc()
2978 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,  in ni_convert_mc_reg_table_to_smc()  argument
2986 		ni_convert_mc_reg_table_entry_to_smc(rdev,  in ni_convert_mc_reg_table_to_smc()
2992 static int ni_populate_mc_reg_table(struct radeon_device *rdev,  in ni_populate_mc_reg_table()  argument
2995 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_populate_mc_reg_table()
2996 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_populate_mc_reg_table()
2997         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_populate_mc_reg_table()
3003 	rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);  in ni_populate_mc_reg_table()
3005 	ni_populate_mc_reg_addresses(rdev, mc_reg_table);  in ni_populate_mc_reg_table()
3007 	ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],  in ni_populate_mc_reg_table()
3015 	ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);  in ni_populate_mc_reg_table()
3017 	return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,  in ni_populate_mc_reg_table()
3023 static int ni_upload_mc_reg_table(struct radeon_device *rdev,  in ni_upload_mc_reg_table()  argument
3026 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_upload_mc_reg_table()
3027 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_upload_mc_reg_table()
3028         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_upload_mc_reg_table()
3035 	ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);  in ni_upload_mc_reg_table()
3040 	return rv770_copy_bytes_to_smc(rdev, address,  in ni_upload_mc_reg_table()
3046 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,  in ni_init_driver_calculated_leakage_table()  argument
3049 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_init_driver_calculated_leakage_table()
3050 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_init_driver_calculated_leakage_table()
3062 	scaling_factor = ni_get_smc_power_scaling_factor(rdev);  in ni_init_driver_calculated_leakage_table()
3071 			ni_calculate_leakage_for_v_and_t(rdev,  in ni_init_driver_calculated_leakage_table()
3093 static int ni_init_simplified_leakage_table(struct radeon_device *rdev,  in ni_init_simplified_leakage_table()  argument
3096 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_init_simplified_leakage_table()
3098 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in ni_init_simplified_leakage_table()
3118 	scaling_factor = ni_get_smc_power_scaling_factor(rdev);  in ni_init_simplified_leakage_table()
3139 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)  in ni_initialize_smc_cac_tables()  argument
3141 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_initialize_smc_cac_tables()
3142 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_initialize_smc_cac_tables()
3165 	ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;  in ni_initialize_smc_cac_tables()
3177 		ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);  in ni_initialize_smc_cac_tables()
3179 		ret = ni_init_simplified_leakage_table(rdev, cac_tables);  in ni_initialize_smc_cac_tables()
3194 	ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,  in ni_initialize_smc_cac_tables()
3208 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)  in ni_initialize_hardware_cac_manager()  argument
3210 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_initialize_hardware_cac_manager()
3377 static int ni_enable_smc_cac(struct radeon_device *rdev,  in ni_enable_smc_cac()  argument
3381 	struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_enable_smc_cac()
3388 				smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);  in ni_enable_smc_cac()
3391 					smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);  in ni_enable_smc_cac()
3396 				smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);  in ni_enable_smc_cac()
3403 			smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);  in ni_enable_smc_cac()
3408 				smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);  in ni_enable_smc_cac()
3418 static int ni_pcie_performance_request(struct radeon_device *rdev,  in ni_pcie_performance_request()  argument
3422 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_pcie_performance_request()
3427 			radeon_acpi_pcie_notify_device_ready(rdev);  in ni_pcie_performance_request()
3429 		return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);  in ni_pcie_performance_request()
3433 		return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);  in ni_pcie_performance_request()
3439 static int ni_advertise_gen2_capability(struct radeon_device *rdev)  in ni_advertise_gen2_capability()  argument
3441 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_advertise_gen2_capability()
3453 		ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);  in ni_advertise_gen2_capability()
3458 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,  in ni_enable_bif_dynamic_pcie_gen2()  argument
3461         struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_enable_bif_dynamic_pcie_gen2()
3497 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,  in ni_enable_dynamic_pcie_gen2()  argument
3500 	ni_enable_bif_dynamic_pcie_gen2(rdev, enable);  in ni_enable_dynamic_pcie_gen2()
3508 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,  in ni_set_uvd_clock_before_set_eng_clock()  argument
3523 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3526 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,  in ni_set_uvd_clock_after_set_eng_clock()  argument
3541 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
3544 void ni_dpm_setup_asic(struct radeon_device *rdev)  in ni_dpm_setup_asic()  argument
3546 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_setup_asic()
3549 	r = ni_mc_load_microcode(rdev);  in ni_dpm_setup_asic()
3552 	ni_read_clock_registers(rdev);  in ni_dpm_setup_asic()
3553 	btc_read_arb_registers(rdev);  in ni_dpm_setup_asic()
3554 	rv770_get_memory_type(rdev);  in ni_dpm_setup_asic()
3556 		ni_advertise_gen2_capability(rdev);  in ni_dpm_setup_asic()
3557 	rv770_get_pcie_gen2_status(rdev);  in ni_dpm_setup_asic()
3558 	rv770_enable_acpi_pm(rdev);  in ni_dpm_setup_asic()
3561 void ni_update_current_ps(struct radeon_device *rdev,  in ni_update_current_ps()  argument
3565 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_update_current_ps()
3566         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_update_current_ps()
3573 void ni_update_requested_ps(struct radeon_device *rdev,  in ni_update_requested_ps()  argument
3577 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_update_requested_ps()
3578         struct ni_power_info *ni_pi = ni_get_pi(rdev);  in ni_update_requested_ps()
3585 int ni_dpm_enable(struct radeon_device *rdev)  in ni_dpm_enable()  argument
3587 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_dpm_enable()
3588 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_enable()
3589 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_enable()
3593 		ni_cg_clockgating_default(rdev);  in ni_dpm_enable()
3594         if (btc_dpm_enabled(rdev))  in ni_dpm_enable()
3597 		ni_mg_clockgating_default(rdev);  in ni_dpm_enable()
3599 		ni_ls_clockgating_default(rdev);  in ni_dpm_enable()
3601 		rv770_enable_voltage_control(rdev, true);  in ni_dpm_enable()
3602 		ret = cypress_construct_voltage_tables(rdev);  in ni_dpm_enable()
3609 		ret = ni_initialize_mc_reg_table(rdev);  in ni_dpm_enable()
3614 		cypress_enable_spread_spectrum(rdev, true);  in ni_dpm_enable()
3616 		rv770_enable_thermal_protection(rdev, true);  in ni_dpm_enable()
3617 	rv770_setup_bsp(rdev);  in ni_dpm_enable()
3618 	rv770_program_git(rdev);  in ni_dpm_enable()
3619 	rv770_program_tp(rdev);  in ni_dpm_enable()
3620 	rv770_program_tpp(rdev);  in ni_dpm_enable()
3621 	rv770_program_sstp(rdev);  in ni_dpm_enable()
3622 	cypress_enable_display_gap(rdev);  in ni_dpm_enable()
3623 	rv770_program_vc(rdev);  in ni_dpm_enable()
3625 		ni_enable_dynamic_pcie_gen2(rdev, true);  in ni_dpm_enable()
3626 	ret = rv770_upload_firmware(rdev);  in ni_dpm_enable()
3631 	ret = ni_process_firmware_header(rdev);  in ni_dpm_enable()
3636 	ret = ni_initial_switch_from_arb_f0_to_f1(rdev);  in ni_dpm_enable()
3641 	ret = ni_init_smc_table(rdev);  in ni_dpm_enable()
3646 	ret = ni_init_smc_spll_table(rdev);  in ni_dpm_enable()
3651 	ret = ni_init_arb_table_index(rdev);  in ni_dpm_enable()
3657 		ret = ni_populate_mc_reg_table(rdev, boot_ps);  in ni_dpm_enable()
3663 	ret = ni_initialize_smc_cac_tables(rdev);  in ni_dpm_enable()
3668 	ret = ni_initialize_hardware_cac_manager(rdev);  in ni_dpm_enable()
3673 	ret = ni_populate_smc_tdp_limits(rdev, boot_ps);  in ni_dpm_enable()
3678 	ni_program_response_times(rdev);  in ni_dpm_enable()
3679 	r7xx_start_smc(rdev);  in ni_dpm_enable()
3680 	ret = cypress_notify_smc_display_change(rdev, false);  in ni_dpm_enable()
3685 	cypress_enable_sclk_control(rdev, true);  in ni_dpm_enable()
3687 		cypress_enable_mclk_control(rdev, true);  in ni_dpm_enable()
3688 	cypress_start_dpm(rdev);  in ni_dpm_enable()
3690 		ni_gfx_clockgating_enable(rdev, true);  in ni_dpm_enable()
3692 		ni_mg_clockgating_enable(rdev, true);  in ni_dpm_enable()
3694 		ni_ls_clockgating_enable(rdev, true);  in ni_dpm_enable()
3696 	rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);  in ni_dpm_enable()
3698 	ni_update_current_ps(rdev, boot_ps);  in ni_dpm_enable()
3703 void ni_dpm_disable(struct radeon_device *rdev)  in ni_dpm_disable()  argument
3705 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_dpm_disable()
3706 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_disable()
3707 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_disable()
3709 	if (!btc_dpm_enabled(rdev))  in ni_dpm_disable()
3711 	rv770_clear_vc(rdev);  in ni_dpm_disable()
3713 		rv770_enable_thermal_protection(rdev, false);  in ni_dpm_disable()
3714 	ni_enable_power_containment(rdev, boot_ps, false);  in ni_dpm_disable()
3715 	ni_enable_smc_cac(rdev, boot_ps, false);  in ni_dpm_disable()
3716 	cypress_enable_spread_spectrum(rdev, false);  in ni_dpm_disable()
3717 	rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);  in ni_dpm_disable()
3719 		ni_enable_dynamic_pcie_gen2(rdev, false);  in ni_dpm_disable()
3721 	if (rdev->irq.installed &&  in ni_dpm_disable()
3722 	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {  in ni_dpm_disable()
3723 		rdev->irq.dpm_thermal = false;  in ni_dpm_disable()
3724 		radeon_irq_set(rdev);  in ni_dpm_disable()
3728 		ni_gfx_clockgating_enable(rdev, false);  in ni_dpm_disable()
3730 		ni_mg_clockgating_enable(rdev, false);  in ni_dpm_disable()
3732 		ni_ls_clockgating_enable(rdev, false);  in ni_dpm_disable()
3733 	ni_stop_dpm(rdev);  in ni_dpm_disable()
3734 	btc_reset_to_default(rdev);  in ni_dpm_disable()
3735 	ni_stop_smc(rdev);  in ni_dpm_disable()
3736 	ni_force_switch_to_arb_f0(rdev);  in ni_dpm_disable()
3738 	ni_update_current_ps(rdev, boot_ps);  in ni_dpm_disable()
3741 static int ni_power_control_set_level(struct radeon_device *rdev)  in ni_power_control_set_level()  argument
3743 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in ni_power_control_set_level()
3746 	ret = ni_restrict_performance_levels_before_switch(rdev);  in ni_power_control_set_level()
3749 	ret = rv770_halt_smc(rdev);  in ni_power_control_set_level()
3752 	ret = ni_populate_smc_tdp_limits(rdev, new_ps);  in ni_power_control_set_level()
3755 	ret = rv770_resume_smc(rdev);  in ni_power_control_set_level()
3758 	ret = rv770_set_sw_state(rdev);  in ni_power_control_set_level()
3765 int ni_dpm_pre_set_power_state(struct radeon_device *rdev)  in ni_dpm_pre_set_power_state()  argument
3767 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_pre_set_power_state()
3768 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in ni_dpm_pre_set_power_state()
3771 	ni_update_requested_ps(rdev, new_ps);  in ni_dpm_pre_set_power_state()
3773 	ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);  in ni_dpm_pre_set_power_state()
3778 int ni_dpm_set_power_state(struct radeon_device *rdev)  in ni_dpm_set_power_state()  argument
3780 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_set_power_state()
3785 	ret = ni_restrict_performance_levels_before_switch(rdev);  in ni_dpm_set_power_state()
3790 	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3791 	ret = ni_enable_power_containment(rdev, new_ps, false);  in ni_dpm_set_power_state()
3796 	ret = ni_enable_smc_cac(rdev, new_ps, false);  in ni_dpm_set_power_state()
3801 	ret = rv770_halt_smc(rdev);  in ni_dpm_set_power_state()
3807 		btc_notify_uvd_to_smc(rdev, new_ps);  in ni_dpm_set_power_state()
3808 	ret = ni_upload_sw_state(rdev, new_ps);  in ni_dpm_set_power_state()
3814 		ret = ni_upload_mc_reg_table(rdev, new_ps);  in ni_dpm_set_power_state()
3820 	ret = ni_program_memory_timing_parameters(rdev, new_ps);  in ni_dpm_set_power_state()
3825 	ret = rv770_resume_smc(rdev);  in ni_dpm_set_power_state()
3830 	ret = rv770_set_sw_state(rdev);  in ni_dpm_set_power_state()
3835 	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3836 	ret = ni_enable_smc_cac(rdev, new_ps, true);  in ni_dpm_set_power_state()
3841 	ret = ni_enable_power_containment(rdev, new_ps, true);  in ni_dpm_set_power_state()
3848 	ret = ni_power_control_set_level(rdev);  in ni_dpm_set_power_state()
3857 void ni_dpm_post_set_power_state(struct radeon_device *rdev)  in ni_dpm_post_set_power_state()  argument
3859 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_post_set_power_state()
3862 	ni_update_current_ps(rdev, new_ps);  in ni_dpm_post_set_power_state()
3866 void ni_dpm_reset_asic(struct radeon_device *rdev)
3868 	ni_restrict_performance_levels_before_switch(rdev);
3869 	rv770_set_boot_state(rdev);
3894 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,  in ni_parse_pplib_non_clock_info()  argument
3915 		rdev->pm.dpm.boot_ps = rps;  in ni_parse_pplib_non_clock_info()
3917 		rdev->pm.dpm.uvd_ps = rps;  in ni_parse_pplib_non_clock_info()
3920 static void ni_parse_pplib_clock_info(struct radeon_device *rdev,  in ni_parse_pplib_clock_info()  argument
3924 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);  in ni_parse_pplib_clock_info()
3925 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_parse_pplib_clock_info()
3969 		radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);  in ni_parse_pplib_clock_info()
3970 		pl->mclk = rdev->clock.default_mclk;  in ni_parse_pplib_clock_info()
3971 		pl->sclk = rdev->clock.default_sclk;  in ni_parse_pplib_clock_info()
3978 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in ni_parse_pplib_clock_info()
3979 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in ni_parse_pplib_clock_info()
3980 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3981 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in ni_parse_pplib_clock_info()
3985 static int ni_parse_power_table(struct radeon_device *rdev)  in ni_parse_power_table()  argument
3987 	struct radeon_mode_info *mode_info = &rdev->mode_info;  in ni_parse_power_table()
4003 	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *  in ni_parse_power_table()
4005 	if (!rdev->pm.dpm.ps)  in ni_parse_power_table()
4022 				kfree(rdev->pm.dpm.ps);  in ni_parse_power_table()
4025 			rdev->pm.dpm.ps[i].ps_priv = ps;  in ni_parse_power_table()
4026 			ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in ni_parse_power_table()
4035 				ni_parse_pplib_clock_info(rdev,  in ni_parse_power_table()
4036 							  &rdev->pm.dpm.ps[i], j,  in ni_parse_power_table()
4041 	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;  in ni_parse_power_table()
4045 int ni_dpm_init(struct radeon_device *rdev)  in ni_dpm_init()  argument
4056 	rdev->pm.dpm.priv = ni_pi;  in ni_dpm_init()
4060 	rv770_get_max_vddc(rdev);  in ni_dpm_init()
4068 	ret = r600_get_platform_caps(rdev);  in ni_dpm_init()
4072 	ret = ni_parse_power_table(rdev);  in ni_dpm_init()
4075 	ret = r600_parse_extended_power_table(rdev);  in ni_dpm_init()
4079 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in ni_dpm_init()
4081 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in ni_dpm_init()
4082 		r600_free_extended_power_table(rdev);  in ni_dpm_init()
4085 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in ni_dpm_init()
4086 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in ni_dpm_init()
4087 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in ni_dpm_init()
4088 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in ni_dpm_init()
4089 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in ni_dpm_init()
4090 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in ni_dpm_init()
4091 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in ni_dpm_init()
4092 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in ni_dpm_init()
4093 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in ni_dpm_init()
4095 	ni_patch_dependency_tables_based_on_leakage(rdev);  in ni_dpm_init()
4097 	if (rdev->pm.dpm.voltage_response_time == 0)  in ni_dpm_init()
4098 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in ni_dpm_init()
4099 	if (rdev->pm.dpm.backbias_response_time == 0)  in ni_dpm_init()
4100 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in ni_dpm_init()
4102 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,  in ni_dpm_init()
4126 	if (rdev->pdev->device == 0x6707) {  in ni_dpm_init()
4138 		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);  in ni_dpm_init()
4141 		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);  in ni_dpm_init()
4144 		radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);  in ni_dpm_init()
4146 	rv770_get_engine_memory_ss(rdev);  in ni_dpm_init()
4163 	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)  in ni_dpm_init()
4181 		radeon_acpi_is_pcie_performance_request_supported(rdev);  in ni_dpm_init()
4194 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;  in ni_dpm_init()
4195 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in ni_dpm_init()
4196 	rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;  in ni_dpm_init()
4197 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);  in ni_dpm_init()
4198 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;  in ni_dpm_init()
4199 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in ni_dpm_init()
4200 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in ni_dpm_init()
4201 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;  in ni_dpm_init()
4208 	switch (rdev->pdev->device) {  in ni_dpm_init()
4258 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ni_dpm_init()
4259 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in ni_dpm_init()
4260 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in ni_dpm_init()
4261 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_dpm_init()
4266 void ni_dpm_fini(struct radeon_device *rdev)  in ni_dpm_fini()  argument
4270 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in ni_dpm_fini()
4271 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in ni_dpm_fini()
4273 	kfree(rdev->pm.dpm.ps);  in ni_dpm_fini()
4274 	kfree(rdev->pm.dpm.priv);  in ni_dpm_fini()
4275 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in ni_dpm_fini()
4276 	r600_free_extended_power_table(rdev);  in ni_dpm_fini()
4279 void ni_dpm_print_power_state(struct radeon_device *rdev,  in ni_dpm_print_power_state()  argument
4291 		if (rdev->family >= CHIP_TAHITI)  in ni_dpm_print_power_state()
4298 	r600_dpm_print_ps_status(rdev, rps);  in ni_dpm_print_power_state()
4301 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,  in ni_dpm_debugfs_print_current_performance_level()  argument
4304 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_debugfs_print_current_performance_level()
4322 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)  in ni_dpm_get_current_sclk()  argument
4324 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_get_current_sclk()
4340 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)  in ni_dpm_get_current_mclk()  argument
4342 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_get_current_mclk()
4358 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)  in ni_dpm_get_sclk()  argument
4360 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_get_sclk()
4369 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)  in ni_dpm_get_mclk()  argument
4371 	struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);  in ni_dpm_get_mclk()