Lines Matching refs:ps
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps() local
737 return ps; in ni_get_ps()
788 struct ni_ps *ps = ni_get_ps(rps); in ni_apply_state_adjust_rules() local
807 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
813 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()
814 if (ps->performance_levels[i].vddci > max_limits->vddci) in ni_apply_state_adjust_rules()
815 ps->performance_levels[i].vddci = max_limits->vddci; in ni_apply_state_adjust_rules()
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
825 ps->performance_levels[0].vddci = in ni_apply_state_adjust_rules()
826 ps->performance_levels[ps->performance_level_count - 1].vddci; in ni_apply_state_adjust_rules()
830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].mclk); in ni_apply_state_adjust_rules()
833 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
836 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in ni_apply_state_adjust_rules()
837 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
843 vddci = ps->performance_levels[0].vddci; in ni_apply_state_adjust_rules()
844 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
847 if (vddci < ps->performance_levels[i].vddci) in ni_apply_state_adjust_rules()
848 vddci = ps->performance_levels[i].vddci; in ni_apply_state_adjust_rules()
850 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
851 ps->performance_levels[i].mclk = mclk; in ni_apply_state_adjust_rules()
852 ps->performance_levels[i].vddci = vddci; in ni_apply_state_adjust_rules()
855 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
856 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in ni_apply_state_adjust_rules()
857 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in ni_apply_state_adjust_rules()
858 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in ni_apply_state_adjust_rules()
859 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in ni_apply_state_adjust_rules()
863 for (i = 1; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
866 &ps->performance_levels[i].mclk); in ni_apply_state_adjust_rules()
868 for (i = 0; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
870 &ps->performance_levels[i]); in ni_apply_state_adjust_rules()
872 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
875 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
877 ps->performance_levels[i].mclk, in ni_apply_state_adjust_rules()
878 max_limits->vddci, &ps->performance_levels[i].vddci); in ni_apply_state_adjust_rules()
880 ps->performance_levels[i].mclk, in ni_apply_state_adjust_rules()
881 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
884 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
887 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
890 &ps->performance_levels[i].vddc, in ni_apply_state_adjust_rules()
891 &ps->performance_levels[i].vddci); in ni_apply_state_adjust_rules()
894 ps->dc_compatible = true; in ni_apply_state_adjust_rules()
895 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()
897 ps->dc_compatible = false; in ni_apply_state_adjust_rules()
899 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) in ni_apply_state_adjust_rules()
900 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; in ni_apply_state_adjust_rules()
907 const u32 *ps = NULL; in ni_cg_clockgating_default() local
909 ps = (const u32 *)&cayman_cgcg_cgls_default; in ni_cg_clockgating_default()
912 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_cg_clockgating_default()
919 const u32 *ps = NULL; in ni_gfx_clockgating_enable() local
922 ps = (const u32 *)&cayman_cgcg_cgls_enable; in ni_gfx_clockgating_enable()
925 ps = (const u32 *)&cayman_cgcg_cgls_disable; in ni_gfx_clockgating_enable()
929 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_gfx_clockgating_enable()
935 const u32 *ps = NULL; in ni_mg_clockgating_default() local
937 ps = (const u32 *)&cayman_mgcg_default; in ni_mg_clockgating_default()
940 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_mg_clockgating_default()
947 const u32 *ps = NULL; in ni_mg_clockgating_enable() local
950 ps = (const u32 *)&cayman_mgcg_enable; in ni_mg_clockgating_enable()
953 ps = (const u32 *)&cayman_mgcg_disable; in ni_mg_clockgating_enable()
957 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_mg_clockgating_enable()
963 const u32 *ps = NULL; in ni_ls_clockgating_default() local
965 ps = (const u32 *)&cayman_sysls_default; in ni_ls_clockgating_default()
968 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_ls_clockgating_default()
975 const u32 *ps = NULL; in ni_ls_clockgating_enable() local
978 ps = (const u32 *)&cayman_sysls_enable; in ni_ls_clockgating_enable()
981 ps = (const u32 *)&cayman_sysls_disable; in ni_ls_clockgating_enable()
985 btc_program_mgcg_hw_sequence(rdev, ps, count); in ni_ls_clockgating_enable()
2298 struct ni_ps *ps = ni_get_ps(radeon_state); in ni_populate_smc_sp() local
2302 for (i = 0; i < ps->performance_level_count - 1; i++) in ni_populate_smc_sp()
2305 smc_state->levels[ps->performance_level_count - 1].bSP = in ni_populate_smc_sp()
3926 struct ni_ps *ps = ni_get_ps(rps); in ni_parse_pplib_clock_info() local
3927 struct rv7xx_pl *pl = &ps->performance_levels[index]; in ni_parse_pplib_clock_info()
3929 ps->performance_level_count = index + 1; in ni_parse_pplib_clock_info()
3949 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in ni_parse_pplib_clock_info()
3996 struct ni_ps *ps; in ni_parse_power_table() local
4003 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in ni_parse_power_table()
4005 if (!rdev->pm.dpm.ps) in ni_parse_power_table()
4020 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); in ni_parse_power_table()
4021 if (ps == NULL) { in ni_parse_power_table()
4022 kfree(rdev->pm.dpm.ps); in ni_parse_power_table()
4025 rdev->pm.dpm.ps[i].ps_priv = ps; in ni_parse_power_table()
4026 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ni_parse_power_table()
4036 &rdev->pm.dpm.ps[i], j, in ni_parse_power_table()
4271 kfree(rdev->pm.dpm.ps[i].ps_priv); in ni_dpm_fini()
4273 kfree(rdev->pm.dpm.ps); in ni_dpm_fini()
4282 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_print_power_state() local
4289 for (i = 0; i < ps->performance_level_count; i++) { in ni_dpm_print_power_state()
4290 pl = &ps->performance_levels[i]; in ni_dpm_print_power_state()
4306 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_debugfs_print_current_performance_level() local
4312 if (current_index >= ps->performance_level_count) { in ni_dpm_debugfs_print_current_performance_level()
4315 pl = &ps->performance_levels[current_index]; in ni_dpm_debugfs_print_current_performance_level()
4326 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_get_current_sclk() local
4332 if (current_index >= ps->performance_level_count) { in ni_dpm_get_current_sclk()
4335 pl = &ps->performance_levels[current_index]; in ni_dpm_get_current_sclk()
4344 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_get_current_mclk() local
4350 if (current_index >= ps->performance_level_count) { in ni_dpm_get_current_mclk()
4353 pl = &ps->performance_levels[current_index]; in ni_dpm_get_current_mclk()