Lines Matching refs:pi
728 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi() local
730 return pi; in ni_get_pi()
773 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_dpm_vblank_too_short() local
776 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; in ni_dpm_vblank_too_short()
992 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_patch_single_dependency_table_based_on_leakage() local
998 if (pi->max_vddc == 0) in ni_patch_single_dependency_table_based_on_leakage()
1000 table->entries[i].v = pi->max_vddc; in ni_patch_single_dependency_table_based_on_leakage()
1099 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_process_firmware_header() local
1108 &tmp, pi->sram_end); in ni_process_firmware_header()
1113 pi->state_table_start = (u16)tmp; in ni_process_firmware_header()
1118 &tmp, pi->sram_end); in ni_process_firmware_header()
1123 pi->soft_regs_start = (u16)tmp; in ni_process_firmware_header()
1128 &tmp, pi->sram_end); in ni_process_firmware_header()
1138 &tmp, pi->sram_end); in ni_process_firmware_header()
1148 &tmp, pi->sram_end); in ni_process_firmware_header()
1158 &tmp, pi->sram_end); in ni_process_firmware_header()
1168 &tmp, pi->sram_end); in ni_process_firmware_header()
1202 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1204 if (pi->gfx_clock_gating) {
1272 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_voltage_tables() local
1283 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { in ni_populate_smc_voltage_tables()
1324 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_mvdd_value() local
1327 if (!pi->mvdd_control) { in ni_populate_mvdd_value()
1333 if (mclk <= pi->mvdd_split_frequency) { in ni_populate_mvdd_value()
1455 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_tdp_limits() local
1493 (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) + in ni_populate_smc_tdp_limits()
1496 sizeof(u32) * 4, pi->sram_end); in ni_populate_smc_tdp_limits()
1571 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_init_arb_table_index() local
1577 &tmp, pi->sram_end); in ni_init_arb_table_index()
1585 tmp, pi->sram_end); in ni_init_arb_table_index()
1595 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_force_switch_to_arb_f0() local
1601 &tmp, pi->sram_end); in ni_force_switch_to_arb_f0()
1641 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_do_program_memory_timing_parameters() local
1658 pi->sram_end); in ni_do_program_memory_timing_parameters()
1686 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_initial_state() local
1756 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); in ni_populate_smc_initial_state()
1758 if (pi->boot_in_gen2) in ni_populate_smc_initial_state()
1763 if (pi->mem_gddr5) { in ni_populate_smc_initial_state()
1768 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
1795 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_acpi_state() local
1815 if (pi->acpi_vddc) { in ni_populate_smc_acpi_state()
1818 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); in ni_populate_smc_acpi_state()
1830 if (pi->pcie_gen2) { in ni_populate_smc_acpi_state()
1831 if (pi->acpi_pcie_gen2) in ni_populate_smc_acpi_state()
1841 pi->min_vddc_in_table, in ni_populate_smc_acpi_state()
1870 if (pi->mem_gddr5) in ni_populate_smc_acpi_state()
1942 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_init_smc_table() local
1974 if (pi->mem_gddr5) in ni_init_smc_table()
1994 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table, in ni_init_smc_table()
1995 sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end); in ni_init_smc_table()
2002 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_calculate_sclk_params() local
2040 if (pi->sclk_ss) { in ni_calculate_sclk_params()
2092 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_init_smc_spll_table() local
2153 sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end); in ni_init_smc_spll_table()
2167 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_mclk_value() local
2213 if (pi->mem_gddr5) { in ni_populate_mclk_value()
2236 if (pi->mclk_ss) { in ni_populate_mclk_value()
2256 dll_speed = rv740_get_dll_speed(pi->mem_gddr5, in ni_populate_mclk_value()
2299 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_sp() local
2303 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in ni_populate_smc_sp()
2306 cpu_to_be32(pi->psp); in ni_populate_smc_sp()
2313 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_convert_power_level_to_smc() local
2321 level->gen2PCIE = pi->pcie_gen2 ? in ni_convert_power_level_to_smc()
2329 if (pi->mclk_stutter_mode_threshold && in ni_convert_power_level_to_smc()
2330 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in ni_convert_power_level_to_smc()
2336 if (pi->mem_gddr5) { in ni_convert_power_level_to_smc()
2337 if (pl->mclk > pi->mclk_edc_enable_threshold) in ni_convert_power_level_to_smc()
2394 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_smc_t() local
2437 a_t |= CG_R(t_l * pi->bsp / 20000); in ni_populate_smc_t()
2441 pi->pbsp : pi->bsp; in ni_populate_smc_t()
2454 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_power_containment_values() local
2487 pi->state_table_start + in ni_populate_power_containment_values()
2491 pi->sram_end); in ni_populate_power_containment_values()
2686 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_upload_sw_state() local
2687 u16 address = pi->state_table_start + in ni_upload_sw_state()
2701 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end); in ni_upload_sw_state()
2712 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_set_mc_special_registers() local
2739 if (!pi->mem_gddr5) in ni_set_mc_special_registers()
2995 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_populate_mc_reg_table() local
3020 pi->sram_end); in ni_populate_mc_reg_table()
3026 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_upload_mc_reg_table() local
3043 pi->sram_end); in ni_upload_mc_reg_table()
3141 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_initialize_smc_cac_tables() local
3195 sizeof(PP_NIslands_CACTABLES), pi->sram_end); in ni_initialize_smc_cac_tables()
3441 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_advertise_gen2_capability() local
3448 pi->pcie_gen2 = true; in ni_advertise_gen2_capability()
3450 pi->pcie_gen2 = false; in ni_advertise_gen2_capability()
3452 if (!pi->pcie_gen2) in ni_advertise_gen2_capability()
3461 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_enable_bif_dynamic_pcie_gen2() local
3469 if (!pi->boot_in_gen2) { in ni_enable_bif_dynamic_pcie_gen2()
3484 if (!pi->boot_in_gen2) { in ni_enable_bif_dynamic_pcie_gen2()
3587 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_dpm_enable() local
3592 if (pi->gfx_clock_gating) in ni_dpm_enable()
3596 if (pi->mg_clock_gating) in ni_dpm_enable()
3600 if (pi->voltage_control) { in ni_dpm_enable()
3613 if (pi->dynamic_ss) in ni_dpm_enable()
3615 if (pi->thermal_protection) in ni_dpm_enable()
3624 if (pi->dynamic_pcie_gen2) in ni_dpm_enable()
3689 if (pi->gfx_clock_gating) in ni_dpm_enable()
3691 if (pi->mg_clock_gating) in ni_dpm_enable()
3705 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_dpm_disable() local
3712 if (pi->thermal_protection) in ni_dpm_disable()
3718 if (pi->dynamic_pcie_gen2) in ni_dpm_disable()
3727 if (pi->gfx_clock_gating) in ni_dpm_disable()
3729 if (pi->mg_clock_gating) in ni_dpm_disable()
3924 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in ni_parse_pplib_clock_info() local
3942 if (pi->max_vddc) in ni_parse_pplib_clock_info()
3943 pl->vddc = pi->max_vddc; in ni_parse_pplib_clock_info()
3947 pi->acpi_vddc = pl->vddc; in ni_parse_pplib_clock_info()
3950 pi->acpi_pcie_gen2 = true; in ni_parse_pplib_clock_info()
3952 pi->acpi_pcie_gen2 = false; in ni_parse_pplib_clock_info()
3960 if (pi->min_vddc_in_table > pl->vddc) in ni_parse_pplib_clock_info()
3961 pi->min_vddc_in_table = pl->vddc; in ni_parse_pplib_clock_info()
3963 if (pi->max_vddc_in_table < pl->vddc) in ni_parse_pplib_clock_info()
3964 pi->max_vddc_in_table = pl->vddc; in ni_parse_pplib_clock_info()
4047 struct rv7xx_power_info *pi; in ni_dpm_init() local
4058 pi = &eg_pi->rv7xx; in ni_dpm_init()
4063 pi->acpi_vddc = 0; in ni_dpm_init()
4065 pi->min_vddc_in_table = 0; in ni_dpm_init()
4066 pi->max_vddc_in_table = 0; in ni_dpm_init()
4105 pi->ref_div = dividers.ref_div + 1; in ni_dpm_init()
4107 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in ni_dpm_init()
4109 pi->rlp = RV770_RLP_DFLT; in ni_dpm_init()
4110 pi->rmp = RV770_RMP_DFLT; in ni_dpm_init()
4111 pi->lhp = RV770_LHP_DFLT; in ni_dpm_init()
4112 pi->lmp = RV770_LMP_DFLT; in ni_dpm_init()
4127 pi->mclk_strobe_mode_threshold = 55000; in ni_dpm_init()
4128 pi->mclk_edc_enable_threshold = 55000; in ni_dpm_init()
4131 pi->mclk_strobe_mode_threshold = 40000; in ni_dpm_init()
4132 pi->mclk_edc_enable_threshold = 40000; in ni_dpm_init()
4137 pi->voltage_control = in ni_dpm_init()
4140 pi->mvdd_control = in ni_dpm_init()
4148 pi->asi = RV770_ASI_DFLT; in ni_dpm_init()
4149 pi->pasi = CYPRESS_HASI_DFLT; in ni_dpm_init()
4150 pi->vrc = CYPRESS_VRC_DFLT; in ni_dpm_init()
4152 pi->power_gating = false; in ni_dpm_init()
4154 pi->gfx_clock_gating = true; in ni_dpm_init()
4156 pi->mg_clock_gating = true; in ni_dpm_init()
4157 pi->mgcgtssm = true; in ni_dpm_init()
4161 pi->dynamic_pcie_gen2 = true; in ni_dpm_init()
4164 pi->thermal_protection = true; in ni_dpm_init()
4166 pi->thermal_protection = false; in ni_dpm_init()
4168 pi->display_gap = true; in ni_dpm_init()
4170 pi->dcodt = true; in ni_dpm_init()
4172 pi->ulps = true; in ni_dpm_init()
4190 pi->mclk_stutter_mode_threshold = 0; in ni_dpm_init()
4192 pi->sram_end = SMC_RAM_END; in ni_dpm_init()