728         struct ni_power_info *pi = rdev->pm.dpm.priv;  in ni_get_pi()
795 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in ni_apply_state_adjust_rules()
801 	if (rdev->pm.dpm.ac_power)  in ni_apply_state_adjust_rules()
802 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_apply_state_adjust_rules()
804 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ni_apply_state_adjust_rules()
806 	if (rdev->pm.dpm.ac_power == false) {  in ni_apply_state_adjust_rules()
873 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in ni_apply_state_adjust_rules()
876 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in ni_apply_state_adjust_rules()
879 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in ni_apply_state_adjust_rules()
882 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in ni_apply_state_adjust_rules()
896 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in ni_apply_state_adjust_rules()
899 		if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)  in ni_apply_state_adjust_rules()
1012 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in ni_patch_dependency_tables_based_on_leakage()
1015 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in ni_patch_dependency_tables_based_on_leakage()
1075 	rdev->pm.dpm.forced_level = level;  in ni_dpm_force_performance_level()
1228 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in ni_program_response_times()
1229 	backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;  in ni_program_response_times()
1346 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&  in ni_get_std_voltage_value()
1347 	    ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))  in ni_get_std_voltage_value()
1348 		*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in ni_get_std_voltage_value()
1438 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in ni_calculate_adjusted_tdp_limits()
1442 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1443 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1445 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1446 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1473 						       rdev->pm.dpm.tdp_adjustment,  in ni_populate_smc_tdp_limits()
1945 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in ni_init_smc_table()
1965 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in ni_init_smc_table()
1968 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)  in ni_init_smc_table()
1971 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in ni_init_smc_table()
2478 					       rdev->pm.dpm.tdp_adjustment,  in ni_populate_power_containment_values()
2553 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in ni_populate_sq_ramping_values()
2575 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in ni_populate_sq_ramping_values()
3098 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in ni_init_simplified_leakage_table()
3165 	ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;  in ni_initialize_smc_cac_tables()
3589 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_enable()
3707 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_disable()
3743 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in ni_power_control_set_level()
3768 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in ni_dpm_pre_set_power_state()
3915 		rdev->pm.dpm.boot_ps = rps;  in ni_parse_pplib_non_clock_info()
3917 		rdev->pm.dpm.uvd_ps = rps;  in ni_parse_pplib_non_clock_info()
3978 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in ni_parse_pplib_clock_info()
3979 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in ni_parse_pplib_clock_info()
3980 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3981 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in ni_parse_pplib_clock_info()
4003 	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *  in ni_parse_power_table()
4005 	if (!rdev->pm.dpm.ps)  in ni_parse_power_table()
4022 				kfree(rdev->pm.dpm.ps);  in ni_parse_power_table()
4025 			rdev->pm.dpm.ps[i].ps_priv = ps;  in ni_parse_power_table()
4026 			ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in ni_parse_power_table()
4036 							  &rdev->pm.dpm.ps[i], j,  in ni_parse_power_table()
4041 	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;  in ni_parse_power_table()
4056 	rdev->pm.dpm.priv = ni_pi;  in ni_dpm_init()
4079 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in ni_dpm_init()
4081 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in ni_dpm_init()
4085 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in ni_dpm_init()
4086 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in ni_dpm_init()
4087 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in ni_dpm_init()
4088 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in ni_dpm_init()
4089 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in ni_dpm_init()
4090 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in ni_dpm_init()
4091 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in ni_dpm_init()
4092 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in ni_dpm_init()
4093 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in ni_dpm_init()
4097 	if (rdev->pm.dpm.voltage_response_time == 0)  in ni_dpm_init()
4098 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in ni_dpm_init()
4099 	if (rdev->pm.dpm.backbias_response_time == 0)  in ni_dpm_init()
4100 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in ni_dpm_init()
4194 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;  in ni_dpm_init()
4195 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in ni_dpm_init()
4196 	rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;  in ni_dpm_init()
4197 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);  in ni_dpm_init()
4198 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;  in ni_dpm_init()
4199 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in ni_dpm_init()
4200 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in ni_dpm_init()
4201 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;  in ni_dpm_init()
4258 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ni_dpm_init()
4259 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in ni_dpm_init()
4260 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in ni_dpm_init()
4261 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_dpm_init()
4270 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in ni_dpm_fini()
4271 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in ni_dpm_fini()
4273 	kfree(rdev->pm.dpm.ps);  in ni_dpm_fini()
4274 	kfree(rdev->pm.dpm.priv);  in ni_dpm_fini()
4275 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in ni_dpm_fini()