30 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
53 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,  in cayman_dma_get_rptr()  argument
58 	if (rdev->wb.enabled) {  in cayman_dma_get_rptr()
59 		rptr = rdev->wb.wb[ring->rptr_offs/4];  in cayman_dma_get_rptr()
80 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,  in cayman_dma_get_wptr()  argument
101 void cayman_dma_set_wptr(struct radeon_device *rdev,  in cayman_dma_set_wptr()  argument
122 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,  in cayman_dma_ring_ib_execute()  argument
125 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in cayman_dma_ring_ib_execute()
128 	if (rdev->wb.enabled) {  in cayman_dma_ring_ib_execute()
157 void cayman_dma_stop(struct radeon_device *rdev)  in cayman_dma_stop()  argument
161 	if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||  in cayman_dma_stop()
162 	    (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))  in cayman_dma_stop()
163 		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);  in cayman_dma_stop()
175 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;  in cayman_dma_stop()
176 	rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;  in cayman_dma_stop()
187 int cayman_dma_resume(struct radeon_device *rdev)  in cayman_dma_resume()  argument
197 			ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];  in cayman_dma_resume()
201 			ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];  in cayman_dma_resume()
223 		       upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);  in cayman_dma_resume()
225 		       ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));  in cayman_dma_resume()
227 		if (rdev->wb.enabled)  in cayman_dma_resume()
250 		r = radeon_ring_test(rdev, ring->idx, ring);  in cayman_dma_resume()
257 	if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||  in cayman_dma_resume()
258 	    (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))  in cayman_dma_resume()
259 		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);  in cayman_dma_resume()
271 void cayman_dma_fini(struct radeon_device *rdev)  in cayman_dma_fini()  argument
273 	cayman_dma_stop(rdev);  in cayman_dma_fini()
274 	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);  in cayman_dma_fini()
275 	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);  in cayman_dma_fini()
287 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)  in cayman_dma_is_lockup()  argument
289 	u32 reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_dma_is_lockup()
298 		radeon_ring_lockup_update(rdev, ring);  in cayman_dma_is_lockup()
301 	return radeon_ring_test_lockup(rdev, ring);  in cayman_dma_is_lockup()
315 void cayman_dma_vm_copy_pages(struct radeon_device *rdev,  in cayman_dma_vm_copy_pages()  argument
353 void cayman_dma_vm_write_pages(struct radeon_device *rdev,  in cayman_dma_vm_write_pages()  argument
374 				value = radeon_vm_map_gart(rdev, addr);  in cayman_dma_vm_write_pages()
401 void cayman_dma_vm_set_pages(struct radeon_device *rdev,  in cayman_dma_vm_set_pages()  argument
449 void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,  in cayman_dma_vm_flush()  argument