Lines Matching refs:ring
1397 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1401 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); in cayman_cp_int_cntl_setup()
1411 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit() local
1412 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1417 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1418 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_fence_ring_emit()
1419 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1420 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1421 radeon_ring_write(ring, 10); /* poll interval */ in cayman_fence_ring_emit()
1423 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1424 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
1425 radeon_ring_write(ring, lower_32_bits(addr)); in cayman_fence_ring_emit()
1426 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1427 radeon_ring_write(ring, fence->seq); in cayman_fence_ring_emit()
1428 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1433 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute() local
1434 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cayman_ring_ib_execute()
1439 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1440 radeon_ring_write(ring, 1); in cayman_ring_ib_execute()
1442 if (ring->rptr_save_reg) { in cayman_ring_ib_execute()
1443 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; in cayman_ring_ib_execute()
1444 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1445 radeon_ring_write(ring, ((ring->rptr_save_reg - in cayman_ring_ib_execute()
1447 radeon_ring_write(ring, next_rptr); in cayman_ring_ib_execute()
1450 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1451 radeon_ring_write(ring, in cayman_ring_ib_execute()
1456 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1457 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in cayman_ring_ib_execute()
1460 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1461 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_ring_ib_execute()
1462 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_ring_ib_execute()
1463 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1464 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ in cayman_ring_ib_execute()
1476 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1481 struct radeon_ring *ring) in cayman_gfx_get_rptr() argument
1486 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1488 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_rptr()
1490 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_rptr()
1500 struct radeon_ring *ring) in cayman_gfx_get_wptr() argument
1504 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_wptr()
1506 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_wptr()
1515 struct radeon_ring *ring) in cayman_gfx_set_wptr() argument
1517 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cayman_gfx_set_wptr()
1518 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1520 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { in cayman_gfx_set_wptr()
1521 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1524 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1558 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start() local
1561 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1566 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1567 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1568 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1569 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1570 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in cayman_cp_start()
1571 radeon_ring_write(ring, 0); in cayman_cp_start()
1572 radeon_ring_write(ring, 0); in cayman_cp_start()
1573 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1577 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1584 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1585 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
1588 radeon_ring_write(ring, cayman_default_state[i]); in cayman_cp_start()
1590 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1591 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
1594 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
1595 radeon_ring_write(ring, 0); in cayman_cp_start()
1598 radeon_ring_write(ring, 0xc0026f00); in cayman_cp_start()
1599 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1600 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1601 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1604 radeon_ring_write(ring, 0xc0036f00); in cayman_cp_start()
1605 radeon_ring_write(ring, 0x00000bc4); in cayman_cp_start()
1606 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1607 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1608 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1610 radeon_ring_write(ring, 0xc0026900); in cayman_cp_start()
1611 radeon_ring_write(ring, 0x00000316); in cayman_cp_start()
1612 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cayman_cp_start()
1613 radeon_ring_write(ring, 0x00000010); /* */ in cayman_cp_start()
1615 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1624 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini() local
1626 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1627 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1667 struct radeon_ring *ring; in cayman_cp_resume() local
1699 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1700 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1715 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1716 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1721 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1724 ring->wptr = 0; in cayman_cp_resume()
1726 WREG32(cp_rb_wptr[i], ring->wptr); in cayman_cp_resume()
1734 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1735 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1736 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1738 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1740 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1741 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1742 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1992 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1999 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
2002 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
2007 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup() local
2067 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_startup()
2083 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_startup()
2084 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_startup()
2127 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2132 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2133 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2138 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2139 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2155 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_startup()
2156 if (ring->ring_size) { in cayman_startup()
2157 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cayman_startup()
2166 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_startup()
2167 if (ring->ring_size) in cayman_startup()
2168 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_startup()
2170 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_startup()
2171 if (ring->ring_size) in cayman_startup()
2172 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_startup()
2249 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init() local
2317 ring->ring_obj = NULL; in cayman_init()
2318 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2320 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2321 ring->ring_obj = NULL; in cayman_init()
2322 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2324 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2325 ring->ring_obj = NULL; in cayman_init()
2326 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2330 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_init()
2331 ring->ring_obj = NULL; in cayman_init()
2332 r600_ring_init(rdev, ring, 4096); in cayman_init()
2338 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_init()
2339 ring->ring_obj = NULL; in cayman_init()
2340 r600_ring_init(rdev, ring, 4096); in cayman_init()
2342 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_init()
2343 ring->ring_obj = NULL; in cayman_init()
2344 r600_ring_init(rdev, ring, 4096); in cayman_init()
2603 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2606 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
2607 radeon_ring_write(ring, pd_addr >> 12); in cayman_vm_flush()
2610 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2611 radeon_ring_write(ring, 0x1); in cayman_vm_flush()
2614 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
2615 radeon_ring_write(ring, 1 << vm_id); in cayman_vm_flush()
2618 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
2619 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in cayman_vm_flush()
2621 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cayman_vm_flush()
2622 radeon_ring_write(ring, 0); in cayman_vm_flush()
2623 radeon_ring_write(ring, 0); /* ref */ in cayman_vm_flush()
2624 radeon_ring_write(ring, 0); /* mask */ in cayman_vm_flush()
2625 radeon_ring_write(ring, 0x20); /* poll interval */ in cayman_vm_flush()
2628 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cayman_vm_flush()
2629 radeon_ring_write(ring, 0x0); in cayman_vm_flush()