Lines Matching refs:rdev
42 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) in tn_smc_rreg() argument
47 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
50 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
54 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in tn_smc_wreg() argument
58 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
61 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
190 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
191 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
192 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
193 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
194 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
195 extern void evergreen_mc_program(struct radeon_device *rdev);
196 extern void evergreen_irq_suspend(struct radeon_device *rdev);
197 extern int evergreen_mc_init(struct radeon_device *rdev);
198 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
199 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
200 extern void evergreen_program_aspm(struct radeon_device *rdev);
201 extern void sumo_rlc_fini(struct radeon_device *rdev);
202 extern int sumo_rlc_init(struct radeon_device *rdev);
203 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
453 static void ni_init_golden_registers(struct radeon_device *rdev) in ni_init_golden_registers() argument
455 switch (rdev->family) { in ni_init_golden_registers()
457 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
460 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
465 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
466 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
467 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
468 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
469 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
470 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
471 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
472 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
473 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
474 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
475 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
476 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
477 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
478 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
479 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
480 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
481 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
482 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
483 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
484 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
487 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
491 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
494 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
634 int ni_mc_load_microcode(struct radeon_device *rdev) in ni_mc_load_microcode() argument
641 if (!rdev->mc_fw) in ni_mc_load_microcode()
644 switch (rdev->family) { in ni_mc_load_microcode()
687 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
697 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
710 int ni_init_microcode(struct radeon_device *rdev) in ni_init_microcode() argument
721 switch (rdev->family) { in ni_init_microcode()
773 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
776 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
779 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
785 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
788 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
791 rdev->me_fw->size, fw_name); in ni_init_microcode()
796 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
799 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
802 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
807 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
809 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
812 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
815 rdev->mc_fw->size, fw_name); in ni_init_microcode()
820 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
822 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
827 release_firmware(rdev->smc_fw); in ni_init_microcode()
828 rdev->smc_fw = NULL; in ni_init_microcode()
830 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
833 rdev->mc_fw->size, fw_name); in ni_init_microcode()
844 release_firmware(rdev->pfp_fw); in ni_init_microcode()
845 rdev->pfp_fw = NULL; in ni_init_microcode()
846 release_firmware(rdev->me_fw); in ni_init_microcode()
847 rdev->me_fw = NULL; in ni_init_microcode()
848 release_firmware(rdev->rlc_fw); in ni_init_microcode()
849 rdev->rlc_fw = NULL; in ni_init_microcode()
850 release_firmware(rdev->mc_fw); in ni_init_microcode()
851 rdev->mc_fw = NULL; in ni_init_microcode()
866 int cayman_get_allowed_info_register(struct radeon_device *rdev, in cayman_get_allowed_info_register() argument
885 int tn_get_temp(struct radeon_device *rdev) in tn_get_temp() argument
896 static void cayman_gpu_init(struct radeon_device *rdev) in cayman_gpu_init() argument
909 switch (rdev->family) { in cayman_gpu_init()
911 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
912 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
913 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
914 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
915 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
916 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
917 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
918 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
919 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
920 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
921 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
922 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
923 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
924 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
925 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
926 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
928 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
929 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
930 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
935 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
936 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
937 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
938 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
939 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
940 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
941 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
944 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
945 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
946 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
947 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
948 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
949 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
950 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
951 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
952 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
953 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
954 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
955 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
956 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
957 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
958 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
959 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
960 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
961 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
962 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
963 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
964 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
965 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
966 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
967 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
968 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
969 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
970 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
971 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
972 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
973 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
974 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
975 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
976 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
977 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
978 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
979 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
980 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
981 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
982 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
983 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
984 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
985 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
987 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
988 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
989 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
990 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
991 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
992 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
994 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
995 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
996 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
997 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
998 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
999 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
1000 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
1002 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
1003 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
1004 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
1022 evergreen_fix_pci_max_read_req_size(rdev); in cayman_gpu_init()
1028 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
1029 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
1030 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1032 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1033 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1034 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1037 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1039 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1041 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1043 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1045 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1047 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1057 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1058 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1061 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1064 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1067 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1070 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1075 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1076 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1080 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1083 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1087 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1091 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1093 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1097 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1109 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1113 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1117 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1123 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1127 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1134 if (ASIC_IS_DCE6(rdev)) in cayman_gpu_init()
1143 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1144 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1154 tmp = r6xx_remap_render_backend(rdev, tmp, in cayman_gpu_init()
1155 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1156 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1162 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1184 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1200 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1201 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1202 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1204 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1205 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1206 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1213 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1256 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1269 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) in cayman_pcie_gart_tlb_flush() argument
1278 static int cayman_pcie_gart_enable(struct radeon_device *rdev) in cayman_pcie_gart_enable() argument
1282 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1283 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1286 r = radeon_gart_table_vram_pin(rdev); in cayman_pcie_gart_enable()
1309 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1310 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1311 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1313 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1330 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1332 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1337 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1354 cayman_pcie_gart_tlb_flush(rdev); in cayman_pcie_gart_enable()
1356 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1357 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1358 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1362 static void cayman_pcie_gart_disable(struct radeon_device *rdev) in cayman_pcie_gart_disable() argument
1367 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1386 radeon_gart_table_vram_unpin(rdev); in cayman_pcie_gart_disable()
1389 static void cayman_pcie_gart_fini(struct radeon_device *rdev) in cayman_pcie_gart_fini() argument
1391 cayman_pcie_gart_disable(rdev); in cayman_pcie_gart_fini()
1392 radeon_gart_table_vram_free(rdev); in cayman_pcie_gart_fini()
1393 radeon_gart_fini(rdev); in cayman_pcie_gart_fini()
1396 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, in cayman_cp_int_cntl_setup() argument
1408 void cayman_fence_ring_emit(struct radeon_device *rdev, in cayman_fence_ring_emit() argument
1411 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit()
1412 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1431 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in cayman_ring_ib_execute() argument
1433 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute()
1467 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) in cayman_cp_enable() argument
1472 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1473 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1476 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1480 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, in cayman_gfx_get_rptr() argument
1485 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1486 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1499 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, in cayman_gfx_get_wptr() argument
1514 void cayman_gfx_set_wptr(struct radeon_device *rdev, in cayman_gfx_set_wptr() argument
1529 static int cayman_cp_load_microcode(struct radeon_device *rdev) in cayman_cp_load_microcode() argument
1534 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1537 cayman_cp_enable(rdev, false); in cayman_cp_load_microcode()
1539 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1545 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1556 static int cayman_cp_start(struct radeon_device *rdev) in cayman_cp_start() argument
1558 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1561 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1569 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1573 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1575 cayman_cp_enable(rdev, true); in cayman_cp_start()
1577 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1615 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1622 static void cayman_cp_fini(struct radeon_device *rdev) in cayman_cp_fini() argument
1624 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1625 cayman_cp_enable(rdev, false); in cayman_cp_fini()
1626 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1627 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1630 static int cayman_cp_resume(struct radeon_device *rdev) in cayman_cp_resume() argument
1691 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1699 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1708 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1715 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1721 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1733 cayman_cp_start(rdev); in cayman_cp_resume()
1734 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1735 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1736 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1738 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1740 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1741 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1742 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1746 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1747 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1752 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) in cayman_gpu_check_soft_reset() argument
1813 if (evergreen_is_display_hung(rdev)) in cayman_gpu_check_soft_reset()
1830 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in cayman_gpu_soft_reset() argument
1839 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1841 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1842 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1844 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1846 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1848 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1870 evergreen_mc_stop(rdev, &save); in cayman_gpu_soft_reset()
1871 if (evergreen_mc_wait_for_idle(rdev)) { in cayman_gpu_soft_reset()
1872 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1920 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1928 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1942 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1956 evergreen_mc_resume(rdev, &save); in cayman_gpu_soft_reset()
1959 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1962 int cayman_asic_reset(struct radeon_device *rdev) in cayman_asic_reset() argument
1966 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1969 r600_set_bios_scratch_engine_hung(rdev, true); in cayman_asic_reset()
1971 cayman_gpu_soft_reset(rdev, reset_mask); in cayman_asic_reset()
1973 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1976 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1978 r600_set_bios_scratch_engine_hung(rdev, false); in cayman_asic_reset()
1992 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1994 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_gfx_is_lockup()
1999 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
2002 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
2005 static int cayman_startup(struct radeon_device *rdev) in cayman_startup() argument
2007 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup()
2011 evergreen_pcie_gen2_enable(rdev); in cayman_startup()
2013 evergreen_program_aspm(rdev); in cayman_startup()
2016 r = r600_vram_scratch_init(rdev); in cayman_startup()
2020 evergreen_mc_program(rdev); in cayman_startup()
2022 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2023 r = ni_mc_load_microcode(rdev); in cayman_startup()
2030 r = cayman_pcie_gart_enable(rdev); in cayman_startup()
2033 cayman_gpu_init(rdev); in cayman_startup()
2036 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2037 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2038 rdev->rlc.reg_list_size = in cayman_startup()
2040 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2041 r = sumo_rlc_init(rdev); in cayman_startup()
2049 r = radeon_wb_init(rdev); in cayman_startup()
2053 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in cayman_startup()
2055 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2059 r = uvd_v2_2_resume(rdev); in cayman_startup()
2061 r = radeon_fence_driver_start_ring(rdev, in cayman_startup()
2064 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); in cayman_startup()
2067 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_startup()
2069 if (rdev->family == CHIP_ARUBA) { in cayman_startup()
2070 r = radeon_vce_resume(rdev); in cayman_startup()
2072 r = vce_v1_0_resume(rdev); in cayman_startup()
2075 r = radeon_fence_driver_start_ring(rdev, in cayman_startup()
2078 r = radeon_fence_driver_start_ring(rdev, in cayman_startup()
2082 dev_err(rdev->dev, "VCE init error (%d).\n", r); in cayman_startup()
2083 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_startup()
2084 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_startup()
2088 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cayman_startup()
2090 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2094 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in cayman_startup()
2096 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2100 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in cayman_startup()
2102 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2106 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in cayman_startup()
2108 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2113 if (!rdev->irq.installed) { in cayman_startup()
2114 r = radeon_irq_kms_init(rdev); in cayman_startup()
2119 r = r600_irq_init(rdev); in cayman_startup()
2122 radeon_irq_kms_fini(rdev); in cayman_startup()
2125 evergreen_irq_set(rdev); in cayman_startup()
2127 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2132 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2133 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2138 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2139 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2144 r = cayman_cp_load_microcode(rdev); in cayman_startup()
2147 r = cayman_cp_resume(rdev); in cayman_startup()
2151 r = cayman_dma_resume(rdev); in cayman_startup()
2155 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_startup()
2157 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cayman_startup()
2160 r = uvd_v1_0_init(rdev); in cayman_startup()
2165 if (rdev->family == CHIP_ARUBA) { in cayman_startup()
2166 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_startup()
2168 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_startup()
2170 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_startup()
2172 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_startup()
2175 r = vce_v1_0_init(rdev); in cayman_startup()
2180 r = radeon_ib_pool_init(rdev); in cayman_startup()
2182 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2186 r = radeon_vm_manager_init(rdev); in cayman_startup()
2188 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2192 r = radeon_audio_init(rdev); in cayman_startup()
2199 int cayman_resume(struct radeon_device *rdev) in cayman_resume() argument
2208 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2211 ni_init_golden_registers(rdev); in cayman_resume()
2213 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2214 radeon_pm_resume(rdev); in cayman_resume()
2216 rdev->accel_working = true; in cayman_resume()
2217 r = cayman_startup(rdev); in cayman_resume()
2220 rdev->accel_working = false; in cayman_resume()
2226 int cayman_suspend(struct radeon_device *rdev) in cayman_suspend() argument
2228 radeon_pm_suspend(rdev); in cayman_suspend()
2229 radeon_audio_fini(rdev); in cayman_suspend()
2230 radeon_vm_manager_fini(rdev); in cayman_suspend()
2231 cayman_cp_enable(rdev, false); in cayman_suspend()
2232 cayman_dma_stop(rdev); in cayman_suspend()
2233 uvd_v1_0_fini(rdev); in cayman_suspend()
2234 radeon_uvd_suspend(rdev); in cayman_suspend()
2235 evergreen_irq_suspend(rdev); in cayman_suspend()
2236 radeon_wb_disable(rdev); in cayman_suspend()
2237 cayman_pcie_gart_disable(rdev); in cayman_suspend()
2247 int cayman_init(struct radeon_device *rdev) in cayman_init() argument
2249 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init()
2253 if (!radeon_get_bios(rdev)) { in cayman_init()
2254 if (ASIC_IS_AVIVO(rdev)) in cayman_init()
2258 if (!rdev->is_atom_bios) { in cayman_init()
2259 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2262 r = radeon_atombios_init(rdev); in cayman_init()
2267 if (!radeon_card_posted(rdev)) { in cayman_init()
2268 if (!rdev->bios) { in cayman_init()
2269 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2273 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2276 ni_init_golden_registers(rdev); in cayman_init()
2278 r600_scratch_init(rdev); in cayman_init()
2280 radeon_surface_init(rdev); in cayman_init()
2282 radeon_get_clock_info(rdev->ddev); in cayman_init()
2284 r = radeon_fence_driver_init(rdev); in cayman_init()
2288 r = evergreen_mc_init(rdev); in cayman_init()
2292 r = radeon_bo_init(rdev); in cayman_init()
2296 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2297 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2298 r = ni_init_microcode(rdev); in cayman_init()
2305 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2306 r = ni_init_microcode(rdev); in cayman_init()
2315 radeon_pm_init(rdev); in cayman_init()
2318 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2320 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2322 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2324 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2326 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2328 r = radeon_uvd_init(rdev); in cayman_init()
2330 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_init()
2332 r600_ring_init(rdev, ring, 4096); in cayman_init()
2335 if (rdev->family == CHIP_ARUBA) { in cayman_init()
2336 r = radeon_vce_init(rdev); in cayman_init()
2338 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_init()
2340 r600_ring_init(rdev, ring, 4096); in cayman_init()
2342 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_init()
2344 r600_ring_init(rdev, ring, 4096); in cayman_init()
2348 rdev->ih.ring_obj = NULL; in cayman_init()
2349 r600_ih_ring_init(rdev, 64 * 1024); in cayman_init()
2351 r = r600_pcie_gart_init(rdev); in cayman_init()
2355 rdev->accel_working = true; in cayman_init()
2356 r = cayman_startup(rdev); in cayman_init()
2358 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2359 cayman_cp_fini(rdev); in cayman_init()
2360 cayman_dma_fini(rdev); in cayman_init()
2361 r600_irq_fini(rdev); in cayman_init()
2362 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2363 sumo_rlc_fini(rdev); in cayman_init()
2364 radeon_wb_fini(rdev); in cayman_init()
2365 radeon_ib_pool_fini(rdev); in cayman_init()
2366 radeon_vm_manager_fini(rdev); in cayman_init()
2367 radeon_irq_kms_fini(rdev); in cayman_init()
2368 cayman_pcie_gart_fini(rdev); in cayman_init()
2369 rdev->accel_working = false; in cayman_init()
2379 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2387 void cayman_fini(struct radeon_device *rdev) in cayman_fini() argument
2389 radeon_pm_fini(rdev); in cayman_fini()
2390 cayman_cp_fini(rdev); in cayman_fini()
2391 cayman_dma_fini(rdev); in cayman_fini()
2392 r600_irq_fini(rdev); in cayman_fini()
2393 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2394 sumo_rlc_fini(rdev); in cayman_fini()
2395 radeon_wb_fini(rdev); in cayman_fini()
2396 radeon_vm_manager_fini(rdev); in cayman_fini()
2397 radeon_ib_pool_fini(rdev); in cayman_fini()
2398 radeon_irq_kms_fini(rdev); in cayman_fini()
2399 uvd_v1_0_fini(rdev); in cayman_fini()
2400 radeon_uvd_fini(rdev); in cayman_fini()
2401 if (rdev->family == CHIP_ARUBA) in cayman_fini()
2402 radeon_vce_fini(rdev); in cayman_fini()
2403 cayman_pcie_gart_fini(rdev); in cayman_fini()
2404 r600_vram_scratch_fini(rdev); in cayman_fini()
2405 radeon_gem_fini(rdev); in cayman_fini()
2406 radeon_fence_driver_fini(rdev); in cayman_fini()
2407 radeon_bo_fini(rdev); in cayman_fini()
2408 radeon_atombios_fini(rdev); in cayman_fini()
2409 kfree(rdev->bios); in cayman_fini()
2410 rdev->bios = NULL; in cayman_fini()
2416 int cayman_vm_init(struct radeon_device *rdev) in cayman_vm_init() argument
2419 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2421 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2424 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2426 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2430 void cayman_vm_fini(struct radeon_device *rdev) in cayman_vm_fini() argument
2443 void cayman_vm_decode_fault(struct radeon_device *rdev, in cayman_vm_decode_fault() argument
2603 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2632 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2637 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in tn_set_vce_clocks()