67 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,  in evergreen_hdmi_update_acr()  argument
80 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,  in evergreen_hdmi_update_acr()
83 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,  in evergreen_hdmi_update_acr()
87 	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));  in evergreen_hdmi_update_acr()
88 	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);  in evergreen_hdmi_update_acr()
90 	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));  in evergreen_hdmi_update_acr()
91 	WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);  in evergreen_hdmi_update_acr()
93 	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));  in evergreen_hdmi_update_acr()
94 	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);  in evergreen_hdmi_update_acr()
208 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,  in evergreen_set_avi_packet()  argument
213 	WREG32(AFMT_AVI_INFO0 + offset,  in evergreen_set_avi_packet()
215 	WREG32(AFMT_AVI_INFO1 + offset,  in evergreen_set_avi_packet()
217 	WREG32(AFMT_AVI_INFO2 + offset,  in evergreen_set_avi_packet()
219 	WREG32(AFMT_AVI_INFO3 + offset,  in evergreen_set_avi_packet()
222 	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,  in evergreen_set_avi_packet()
306 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)  in dce4_set_vbi_packet()  argument
311 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,  in dce4_set_vbi_packet()
317 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)  in dce4_hdmi_set_color_depth()  argument
324 	val = RREG32(HDMI_CONTROL + offset);  in dce4_hdmi_set_color_depth()
351 	WREG32(HDMI_CONTROL + offset, val);  in dce4_hdmi_set_color_depth()
354 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)  in dce4_set_audio_packet()  argument
359 	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,  in dce4_set_audio_packet()
362 	WREG32(AFMT_60958_0 + offset,  in dce4_set_audio_packet()
365 	WREG32(AFMT_60958_1 + offset,  in dce4_set_audio_packet()
368 	WREG32(AFMT_60958_2 + offset,  in dce4_set_audio_packet()
376 	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,  in dce4_set_audio_packet()
379 	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,  in dce4_set_audio_packet()
384 	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,  in dce4_set_audio_packet()
389 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)  in dce4_set_mute()  argument
395 		WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);  in dce4_set_mute()
397 		WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);  in dce4_set_mute()
414 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,  in evergreen_hdmi_enable()
419 			WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
422 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,  in evergreen_hdmi_enable()
425 			WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
429 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
431 		WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);  in evergreen_hdmi_enable()
437 		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);  in evergreen_hdmi_enable()
458 		WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_dp_enable()
461 		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,  in evergreen_dp_enable()
466 			val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);  in evergreen_dp_enable()
474 			WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);  in evergreen_dp_enable()
477 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,  in evergreen_dp_enable()
483 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);  in evergreen_dp_enable()
484 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_dp_enable()