1823 		ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in evergreen_packet3_check()
1869 		ib[idx+1] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
1904 		ib[idx+1] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
1932 		ib[idx+2] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2025 		ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;  in evergreen_packet3_check()
2105 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2166 				ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in evergreen_packet3_check()
2204 				ib[idx+3] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2246 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2268 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in evergreen_packet3_check()
2290 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);  in evergreen_packet3_check()
2420 						    (upper_32_bits(offset64) & 0xff);  in evergreen_packet3_check()
2500 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2519 			ib[idx+4] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2548 		ib[idx+1] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2573 			ib[idx+2] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2600 			ib[idx+4] = upper_32_bits(offset) & 0xff;  in evergreen_packet3_check()
2789 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2833 				ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2834 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2849 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2855 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2892 				ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2893 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2904 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2906 				ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2942 				ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2943 				ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2944 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2982 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2998 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3002 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3044 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3060 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3066 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3131 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3153 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in evergreen_dma_cs_parse()