2752 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2817 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2818 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2821 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2823 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2842 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2843 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2852 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2853 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2861 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2863 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2876 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2877 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2880 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2882 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2922 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
2923 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2924 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2926 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2962 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
2963 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2964 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2966 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3024 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3025 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3026 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3028 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3053 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3054 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3063 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3064 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3072 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3074 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3111 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3112 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3113 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3115 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()