Lines Matching refs:reloc
1097 struct radeon_bo_list *reloc; in evergreen_cs_handle_reg() local
1143 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1172 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1185 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1214 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1222 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1226 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1234 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1238 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1246 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1250 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1258 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1273 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1282 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1295 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1359 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1438 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1448 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1466 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1476 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1499 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1505 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1516 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1522 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1554 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1563 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1579 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1583 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1591 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1701 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1729 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1774 struct radeon_bo_list *reloc; in evergreen_packet3_check() local
1812 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1818 offset = reloc->gpu_offset + in evergreen_packet3_check()
1858 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1864 offset = reloc->gpu_offset + in evergreen_packet3_check()
1893 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1899 offset = reloc->gpu_offset + in evergreen_packet3_check()
1921 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1927 offset = reloc->gpu_offset + in evergreen_packet3_check()
2016 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2073 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2094 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2100 offset = reloc->gpu_offset + in evergreen_packet3_check()
2148 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2157 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2159 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2161 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2186 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2195 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2197 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2199 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2220 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2225 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2236 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2241 offset = reloc->gpu_offset + in evergreen_packet3_check()
2257 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2263 offset = reloc->gpu_offset + in evergreen_packet3_check()
2279 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2285 offset = reloc->gpu_offset + in evergreen_packet3_check()
2348 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2355 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_packet3_check()
2356 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
2359 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_packet3_check()
2370 texture = reloc->robj; in evergreen_packet3_check()
2371 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2385 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2390 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2391 mipmap = reloc->robj; in evergreen_packet3_check()
2404 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2411 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2414 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2417 offset64 = reloc->gpu_offset + offset; in evergreen_packet3_check()
2486 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2493 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2495 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2498 offset += reloc->gpu_offset; in evergreen_packet3_check()
2505 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2512 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2514 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2517 offset += reloc->gpu_offset; in evergreen_packet3_check()
2530 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2541 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2543 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2546 offset += reloc->gpu_offset; in evergreen_packet3_check()
2559 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2566 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2568 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2571 offset += reloc->gpu_offset; in evergreen_packet3_check()
2586 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2593 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2595 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2598 offset += reloc->gpu_offset; in evergreen_packet3_check()