Lines Matching refs:ib
450 uint32_t *ib = p->ib.ptr; in evergreen_cs_track_validate_cb() local
472 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
1098 u32 tmp, *ib; in evergreen_cs_handle_reg() local
1101 ib = p->ib.ptr; in evergreen_cs_handle_reg()
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1178 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1459 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1487 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1598 ib[idx] |= 3; in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1776 uint32_t *ib; in evergreen_packet3_check() local
1784 ib = p->ib.ptr; in evergreen_packet3_check()
1822 ib[idx + 0] = offset; in evergreen_packet3_check()
1823 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1868 ib[idx+0] = offset; in evergreen_packet3_check()
1869 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1903 ib[idx+0] = offset; in evergreen_packet3_check()
1904 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1931 ib[idx+1] = offset; in evergreen_packet3_check()
1932 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2104 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2105 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2165 ib[idx] = offset; in evergreen_packet3_check()
2166 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2203 ib[idx+2] = offset; in evergreen_packet3_check()
2204 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2225 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2245 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2246 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2267 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2268 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2289 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2290 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2354 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2362 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2363 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2374 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2375 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2397 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2398 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2414 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2418 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2419 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2499 ib[idx+1] = offset; in evergreen_packet3_check()
2500 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2518 ib[idx+3] = offset; in evergreen_packet3_check()
2519 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2547 ib[idx+0] = offset; in evergreen_packet3_check()
2548 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2572 ib[idx+1] = offset; in evergreen_packet3_check()
2573 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2599 ib[idx+3] = offset; in evergreen_packet3_check()
2600 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2726 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2727 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_cs_parse()
2750 uint32_t *ib = p->ib.ptr; in evergreen_dma_cs_parse() local
2780 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2788 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2789 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2832 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2833 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2834 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2844 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2848 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2849 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2854 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2855 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2859 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2890 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2891 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2892 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2893 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2903 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2904 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2905 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2906 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2939 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2940 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2941 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2942 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2943 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2944 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2979 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2980 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2981 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2982 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2995 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2997 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2998 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3001 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3002 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3004 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3041 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3042 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3043 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3044 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3055 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3059 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3060 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3065 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3066 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3070 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3091 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3092 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3128 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3129 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3130 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3131 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3152 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3153 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3165 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3166 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_dma_cs_parse()
3297 u32 *ib, struct radeon_cs_packet *pkt) in evergreen_vm_packet3_check() argument
3300 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3356 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3363 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3384 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3385 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3422 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3447 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ib_parse() argument
3455 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3456 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3467 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3468 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); in evergreen_ib_parse()
3478 } while (idx < ib->length_dw); in evergreen_ib_parse()
3492 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_dma_ib_parse() argument
3498 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3515 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3566 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3580 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()