Lines Matching refs:dst_reloc
2748 struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc; in evergreen_dma_cs_parse() local
2769 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2780 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2788 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2789 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2796 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2798 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2808 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2826 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2828 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2833 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2848 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2849 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2859 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2866 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2868 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2885 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2887 dst_offset + count, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2890 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2892 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2905 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2906 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2929 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2931 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2939 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2942 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2969 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2971 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2979 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2997 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2998 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3004 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3031 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3033 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3041 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3059 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3060 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3070 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3077 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3079 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3092 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3118 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3120 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3128 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3140 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
3147 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3149 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3152 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3153 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()