2752 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2777 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2778 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2785 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2786 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2796 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2798 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2819 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2820 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2826 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2828 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2846 					dst_offset = radeon_get_ib_value(p, idx + 7);  in evergreen_dma_cs_parse()
2847 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2857 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2858 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
2866 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2868 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2878 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2879 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2885 				if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2887 							dst_offset + count, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2918 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2919 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2929 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2931 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2958 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2959 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2969 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2971 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3020 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3021 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3031 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3033 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3057 					dst_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3058 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3068 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3069 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
3077 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3079 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3107 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3108 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3118 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3120 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3145 			dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3146 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in evergreen_dma_cs_parse()
3147 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3149 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()