2748 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2913 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
2934 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
2936 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
2940 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2943 				ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2953 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
2974 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
2976 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
2980 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3015 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3036 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3038 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3042 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3102 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3123 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3125 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3129 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()