Lines Matching refs:tmp
1295 u32 tmp = 0; in dce4_program_fmt() local
1320 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | in dce4_program_fmt()
1323 tmp |= FMT_TRUNCATE_EN; in dce4_program_fmt()
1328 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | in dce4_program_fmt()
1332 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); in dce4_program_fmt()
1340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1665 u32 tmp; in evergreen_pm_prepare() local
1671 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1672 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_pm_prepare()
1673 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1690 u32 tmp; in evergreen_pm_finish() local
1696 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1697 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_pm_finish()
1698 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1759 u32 tmp; in evergreen_hpd_set_polarity() local
1764 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity()
1766 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1768 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1769 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1772 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_hpd_set_polarity()
1774 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1776 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1777 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1780 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_hpd_set_polarity()
1782 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1784 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1785 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1788 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_hpd_set_polarity()
1790 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1792 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1793 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1796 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_hpd_set_polarity()
1798 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1800 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1801 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1804 tmp = RREG32(DC_HPD6_INT_CONTROL); in evergreen_hpd_set_polarity()
1806 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1808 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1809 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1829 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | in evergreen_hpd_init() local
1846 WREG32(DC_HPD1_CONTROL, tmp); in evergreen_hpd_init()
1849 WREG32(DC_HPD2_CONTROL, tmp); in evergreen_hpd_init()
1852 WREG32(DC_HPD3_CONTROL, tmp); in evergreen_hpd_init()
1855 WREG32(DC_HPD4_CONTROL, tmp); in evergreen_hpd_init()
1858 WREG32(DC_HPD5_CONTROL, tmp); in evergreen_hpd_init()
1861 WREG32(DC_HPD6_CONTROL, tmp); in evergreen_hpd_init()
1922 u32 tmp, buffer_alloc, i; in evergreen_line_buffer_adjust() local
1947 tmp = 0; /* 1/2 */ in evergreen_line_buffer_adjust()
1950 tmp = 2; /* whole */ in evergreen_line_buffer_adjust()
1954 tmp = 0; in evergreen_line_buffer_adjust()
1960 tmp += 4; in evergreen_line_buffer_adjust()
1961 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1975 switch (tmp) { in evergreen_line_buffer_adjust()
2010 u32 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_get_number_of_dram_channels() local
2012 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in evergreen_get_number_of_dram_channels()
2266 u32 tmp, arb_control3; in evergreen_program_watermarks() local
2382 tmp = arb_control3; in evergreen_program_watermarks()
2383 tmp &= ~LATENCY_WATERMARK_MASK(3); in evergreen_program_watermarks()
2384 tmp |= LATENCY_WATERMARK_MASK(1); in evergreen_program_watermarks()
2385 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2390 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2391 tmp &= ~LATENCY_WATERMARK_MASK(3); in evergreen_program_watermarks()
2392 tmp |= LATENCY_WATERMARK_MASK(2); in evergreen_program_watermarks()
2393 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2456 u32 tmp; in evergreen_mc_wait_for_idle() local
2460 tmp = RREG32(SRBM_STATUS) & 0x1F00; in evergreen_mc_wait_for_idle()
2461 if (!tmp) in evergreen_mc_wait_for_idle()
2474 u32 tmp; in evergreen_pcie_gart_tlb_flush() local
2481 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in evergreen_pcie_gart_tlb_flush()
2482 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; in evergreen_pcie_gart_tlb_flush()
2483 if (tmp == 2) { in evergreen_pcie_gart_tlb_flush()
2487 if (tmp) { in evergreen_pcie_gart_tlb_flush()
2496 u32 tmp; in evergreen_pcie_gart_enable() local
2513 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2518 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2519 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2520 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2522 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2523 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2524 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2529 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2531 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2532 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2533 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2534 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2554 u32 tmp; in evergreen_pcie_gart_disable() local
2566 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); in evergreen_pcie_gart_disable()
2567 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2568 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2569 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2570 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2571 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2572 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2573 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_disable()
2587 u32 tmp; in evergreen_agp_enable() local
2596 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()
2600 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2601 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2602 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2603 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2604 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2605 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2606 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_agp_enable()
2754 u32 crtc_enabled, tmp, frame_count, blackout; in evergreen_mc_stop() local
2771 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2772 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { in evergreen_mc_stop()
2775 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; in evergreen_mc_stop()
2776 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2780 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2781 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { in evergreen_mc_stop()
2784 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_mc_stop()
2785 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2809 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2810 tmp &= ~EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2811 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2836 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2837 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) { in evergreen_mc_stop()
2838 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_mc_stop()
2839 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2841 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_stop()
2842 if (!(tmp & 1)) { in evergreen_mc_stop()
2843 tmp |= 1; in evergreen_mc_stop()
2844 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_stop()
2852 u32 tmp, frame_count; in evergreen_mc_resume() local
2875 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); in evergreen_mc_resume()
2876 if ((tmp & 0x7) != 3) { in evergreen_mc_resume()
2877 tmp &= ~0x7; in evergreen_mc_resume()
2878 tmp |= 0x3; in evergreen_mc_resume()
2879 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2881 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2882 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { in evergreen_mc_resume()
2883 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_mc_resume()
2884 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2886 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_resume()
2887 if (tmp & 1) { in evergreen_mc_resume()
2888 tmp &= ~1; in evergreen_mc_resume()
2889 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_resume()
2892 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2893 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) in evergreen_mc_resume()
2901 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_resume()
2902 tmp &= ~BLACKOUT_MODE_MASK; in evergreen_mc_resume()
2903 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); in evergreen_mc_resume()
2910 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2911 tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN; in evergreen_mc_resume()
2913 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2916 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2917 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_mc_resume()
2919 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2942 u32 tmp; in evergreen_mc_program() local
2987 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; in evergreen_mc_program()
2988 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; in evergreen_mc_program()
2989 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
2990 WREG32(MC_FUS_VM_FB_OFFSET, tmp); in evergreen_mc_program()
2992 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in evergreen_mc_program()
2993 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in evergreen_mc_program()
2994 WREG32(MC_VM_FB_LOCATION, tmp); in evergreen_mc_program()
3155 u32 tmp; in evergreen_cp_resume() local
3173 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in evergreen_cp_resume()
3175 tmp |= BUF_SWAP_32BIT; in evergreen_cp_resume()
3177 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3185 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in evergreen_cp_resume()
3199 tmp |= RB_NO_UPDATE; in evergreen_cp_resume()
3204 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3239 u32 hdp_host_path_cntl, tmp; in evergreen_gpu_init() local
3547 tmp = (((efuse_straps_4 & 0xf) << 4) | in evergreen_gpu_init()
3550 tmp = 0; in evergreen_gpu_init()
3557 tmp <<= 4; in evergreen_gpu_init()
3558 tmp |= rb_disable_bitmap; in evergreen_gpu_init()
3562 disabled_rb_mask = tmp; in evergreen_gpu_init()
3563 tmp = 0; in evergreen_gpu_init()
3565 tmp |= (1 << i); in evergreen_gpu_init()
3567 if ((disabled_rb_mask & tmp) == tmp) { in evergreen_gpu_init()
3579 tmp <<= 16; in evergreen_gpu_init()
3580 tmp |= simd_disable_bitmap; in evergreen_gpu_init()
3582 rdev->config.evergreen.active_simds = hweight32(~tmp); in evergreen_gpu_init()
3599 tmp = 0x11111111; in evergreen_gpu_init()
3602 tmp = 0x00000000; in evergreen_gpu_init()
3605 tmp = gb_addr_config & NUM_PIPES_MASK; in evergreen_gpu_init()
3606 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, in evergreen_gpu_init()
3609 WREG32(GB_BACKEND_MAP, tmp); in evergreen_gpu_init()
3785 tmp = RREG32(HDP_MISC_CNTL); in evergreen_gpu_init()
3786 tmp |= HDP_FLUSH_INVALIDATE_CACHE; in evergreen_gpu_init()
3787 WREG32(HDP_MISC_CNTL, tmp); in evergreen_gpu_init()
3800 u32 tmp; in evergreen_mc_init() local
3808 tmp = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_mc_init()
3810 tmp = RREG32(MC_ARB_RAMCFG); in evergreen_mc_init()
3811 if (tmp & CHANSIZE_OVERRIDE) { in evergreen_mc_init()
3813 } else if (tmp & CHANSIZE_MASK) { in evergreen_mc_init()
3818 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_mc_init()
3819 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in evergreen_mc_init()
3889 u32 i, j, tmp; in evergreen_is_display_hung() local
3901 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3902 if (tmp != crtc_status[i]) in evergreen_is_display_hung()
3917 u32 tmp; in evergreen_gpu_check_soft_reset() local
3920 tmp = RREG32(GRBM_STATUS); in evergreen_gpu_check_soft_reset()
3921 if (tmp & (PA_BUSY | SC_BUSY | in evergreen_gpu_check_soft_reset()
3928 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | in evergreen_gpu_check_soft_reset()
3932 if (tmp & GRBM_EE_BUSY) in evergreen_gpu_check_soft_reset()
3936 tmp = RREG32(DMA_STATUS_REG); in evergreen_gpu_check_soft_reset()
3937 if (!(tmp & DMA_IDLE)) in evergreen_gpu_check_soft_reset()
3941 tmp = RREG32(SRBM_STATUS2); in evergreen_gpu_check_soft_reset()
3942 if (tmp & DMA_BUSY) in evergreen_gpu_check_soft_reset()
3946 tmp = RREG32(SRBM_STATUS); in evergreen_gpu_check_soft_reset()
3947 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) in evergreen_gpu_check_soft_reset()
3950 if (tmp & IH_BUSY) in evergreen_gpu_check_soft_reset()
3953 if (tmp & SEM_BUSY) in evergreen_gpu_check_soft_reset()
3956 if (tmp & GRBM_RQ_PENDING) in evergreen_gpu_check_soft_reset()
3959 if (tmp & VMC_BUSY) in evergreen_gpu_check_soft_reset()
3962 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | in evergreen_gpu_check_soft_reset()
3970 tmp = RREG32(VM_L2_STATUS); in evergreen_gpu_check_soft_reset()
3971 if (tmp & L2_BUSY) in evergreen_gpu_check_soft_reset()
3987 u32 tmp; in evergreen_gpu_soft_reset() local
4001 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
4002 tmp &= ~DMA_RB_ENABLE; in evergreen_gpu_soft_reset()
4003 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4061 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4062 tmp |= grbm_soft_reset; in evergreen_gpu_soft_reset()
4063 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4064 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4065 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4069 tmp &= ~grbm_soft_reset; in evergreen_gpu_soft_reset()
4070 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4071 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4075 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4076 tmp |= srbm_soft_reset; in evergreen_gpu_soft_reset()
4077 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4078 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4079 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4083 tmp &= ~srbm_soft_reset; in evergreen_gpu_soft_reset()
4084 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4085 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4100 u32 tmp, i; in evergreen_gpu_pci_config_reset() local
4110 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4111 tmp &= ~DMA_RB_ENABLE; in evergreen_gpu_pci_config_reset()
4112 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
4481 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_rlc_resume() local
4482 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in evergreen_rlc_resume()
4483 tmp = hweight32(~tmp); in evergreen_rlc_resume()
4484 if (tmp == rdev->config.cayman.max_simds_per_se) { in evergreen_rlc_resume()
4543 u32 tmp; in evergreen_disable_interrupt_state() local
4550 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4551 WREG32(CAYMAN_DMA1_CNTL, tmp); in evergreen_disable_interrupt_state()
4554 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4555 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4585 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4586 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4587 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4588 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4589 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4590 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4591 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4592 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4593 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4594 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4595 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4596 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4832 u32 tmp; in evergreen_irq_ack() local
4902 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4903 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4904 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4907 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4908 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4909 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4912 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4913 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4914 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4917 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4918 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4919 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4922 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4923 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4924 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4927 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4928 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4929 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4933 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4934 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4935 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4938 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4939 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4940 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4943 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4944 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4945 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4948 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4949 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4950 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4953 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4954 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4955 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4958 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4959 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4960 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4964 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4965 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4966 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4969 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4970 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4971 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4974 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4975 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4976 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4979 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4980 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4981 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4984 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4985 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4986 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4989 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4990 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4991 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
5012 u32 wptr, tmp; in evergreen_get_ih_wptr() local
5028 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
5029 tmp |= IH_WPTR_OVERFLOW_CLEAR; in evergreen_get_ih_wptr()
5030 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()