4198 	if (rdev->rlc.save_restore_obj) {  in sumo_rlc_fini()
4199 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_fini()
4202 		radeon_bo_unpin(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4203 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4205 		radeon_bo_unref(&rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4206 		rdev->rlc.save_restore_obj = NULL;  in sumo_rlc_fini()
4210 	if (rdev->rlc.clear_state_obj) {  in sumo_rlc_fini()
4211 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_fini()
4214 		radeon_bo_unpin(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4215 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4217 		radeon_bo_unref(&rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4218 		rdev->rlc.clear_state_obj = NULL;  in sumo_rlc_fini()
4222 	if (rdev->rlc.cp_table_obj) {  in sumo_rlc_fini()
4223 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_fini()
4226 		radeon_bo_unpin(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4227 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4229 		radeon_bo_unref(&rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4230 		rdev->rlc.cp_table_obj = NULL;  in sumo_rlc_fini()
4246 	src_ptr = rdev->rlc.reg_list;  in sumo_rlc_init()
4247 	dws = rdev->rlc.reg_list_size;  in sumo_rlc_init()
4251 	cs_data = rdev->rlc.cs_data;  in sumo_rlc_init()
4255 		if (rdev->rlc.save_restore_obj == NULL) {  in sumo_rlc_init()
4258 					     NULL, &rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4265 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_init()
4270 		r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4271 				  &rdev->rlc.save_restore_gpu_addr);  in sumo_rlc_init()
4273 			radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4279 		r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);  in sumo_rlc_init()
4286 		dst_ptr = rdev->rlc.sr_ptr;  in sumo_rlc_init()
4289 			for (i = 0; i < rdev->rlc.reg_list_size; i++)  in sumo_rlc_init()
4309 		radeon_bo_kunmap(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4310 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4316 			rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);  in sumo_rlc_init()
4318 			rdev->rlc.clear_state_size = si_get_csb_size(rdev);  in sumo_rlc_init()
4319 			dws = rdev->rlc.clear_state_size + (256 / 4);  in sumo_rlc_init()
4331 			rdev->rlc.clear_state_size = dws;  in sumo_rlc_init()
4334 		if (rdev->rlc.clear_state_obj == NULL) {  in sumo_rlc_init()
4337 					     NULL, &rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4344 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_init()
4349 		r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4350 				  &rdev->rlc.clear_state_gpu_addr);  in sumo_rlc_init()
4352 			radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4358 		r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);  in sumo_rlc_init()
4365 		dst_ptr = rdev->rlc.cs_ptr;  in sumo_rlc_init()
4369 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;  in sumo_rlc_init()
4372 			dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);  in sumo_rlc_init()
4376 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);  in sumo_rlc_init()
4405 		radeon_bo_kunmap(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4406 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4409 	if (rdev->rlc.cp_table_size) {  in sumo_rlc_init()
4410 		if (rdev->rlc.cp_table_obj == NULL) {  in sumo_rlc_init()
4411 			r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,  in sumo_rlc_init()
4414 					     NULL, &rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4422 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_init()
4428 		r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4429 				  &rdev->rlc.cp_table_gpu_addr);  in sumo_rlc_init()
4431 			radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4436 		r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);  in sumo_rlc_init()
4445 		radeon_bo_kunmap(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4446 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4495 		WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);  in evergreen_rlc_resume()
4496 		WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);  in evergreen_rlc_resume()
5554 		rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;  in evergreen_startup()
5555 		rdev->rlc.reg_list_size =  in evergreen_startup()
5557 		rdev->rlc.cs_data = evergreen_cs_data;  in evergreen_startup()