3916 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()  local
3926 		reset_mask |= RADEON_RESET_GFX;  in evergreen_gpu_check_soft_reset()
3930 		reset_mask |= RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3933 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3938 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3943 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3948 		reset_mask |= RADEON_RESET_RLC;  in evergreen_gpu_check_soft_reset()
3951 		reset_mask |= RADEON_RESET_IH;  in evergreen_gpu_check_soft_reset()
3954 		reset_mask |= RADEON_RESET_SEM;  in evergreen_gpu_check_soft_reset()
3957 		reset_mask |= RADEON_RESET_GRBM;  in evergreen_gpu_check_soft_reset()
3960 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3964 		reset_mask |= RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3967 		reset_mask |= RADEON_RESET_DISPLAY;  in evergreen_gpu_check_soft_reset()
3972 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3975 	if (reset_mask & RADEON_RESET_MC) {  in evergreen_gpu_check_soft_reset()
3976 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3977 		reset_mask &= ~RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3980 	return reset_mask;  in evergreen_gpu_check_soft_reset()
3983 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in evergreen_gpu_soft_reset()  argument
3989 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3992 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3999 	if (reset_mask & RADEON_RESET_DMA) {  in evergreen_gpu_soft_reset()
4013 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in evergreen_gpu_soft_reset()
4027 	if (reset_mask & RADEON_RESET_CP) {  in evergreen_gpu_soft_reset()
4034 	if (reset_mask & RADEON_RESET_DMA)  in evergreen_gpu_soft_reset()
4037 	if (reset_mask & RADEON_RESET_DISPLAY)  in evergreen_gpu_soft_reset()
4040 	if (reset_mask & RADEON_RESET_RLC)  in evergreen_gpu_soft_reset()
4043 	if (reset_mask & RADEON_RESET_SEM)  in evergreen_gpu_soft_reset()
4046 	if (reset_mask & RADEON_RESET_IH)  in evergreen_gpu_soft_reset()
4049 	if (reset_mask & RADEON_RESET_GRBM)  in evergreen_gpu_soft_reset()
4052 	if (reset_mask & RADEON_RESET_VMC)  in evergreen_gpu_soft_reset()
4056 		if (reset_mask & RADEON_RESET_MC)  in evergreen_gpu_soft_reset()
4141 	u32 reset_mask;  in evergreen_asic_reset()  local
4143 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4145 	if (reset_mask)  in evergreen_asic_reset()
4149 	evergreen_gpu_soft_reset(rdev, reset_mask);  in evergreen_asic_reset()
4151 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4154 	if (reset_mask && radeon_hard_reset)  in evergreen_asic_reset()
4157 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4159 	if (!reset_mask)  in evergreen_asic_reset()
4176 	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_gfx_is_lockup()  local
4178 	if (!(reset_mask & (RADEON_RESET_GFX |  in evergreen_gfx_is_lockup()