1292 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()  local
1340 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1412 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()  local
1415 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1417 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1420 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1433 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()  local
1436 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1664 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_prepare()  local
1669 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_prepare()
1670 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1671 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1673 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1689 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_finish()  local
1694 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_finish()
1695 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1696 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1698 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1918 					struct radeon_crtc *radeon_crtc,  in evergreen_line_buffer_adjust()  argument
1923 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1945 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1959 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1961 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1974 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
2253 					 struct radeon_crtc *radeon_crtc,  in evergreen_program_watermarks()  argument
2256 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2265 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2269 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2294 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2296 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2321 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2323 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2357 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2369 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2377 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in evergreen_program_watermarks()
2401 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2402 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2405 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2406 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2407 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()