Lines Matching refs:WREG32
47 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
58 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
59 WREG32(EVERGREEN_CG_IND_DATA, (v)); in eg_cg_wreg()
69 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
80 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
81 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); in eg_pif_phy0_wreg()
91 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
102 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
103 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); in eg_pif_phy1_wreg()
1179 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
1340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1415 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1417 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1673 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1698 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1769 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1777 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1785 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1793 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1801 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1809 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1846 WREG32(DC_HPD1_CONTROL, tmp); in evergreen_hpd_init()
1849 WREG32(DC_HPD2_CONTROL, tmp); in evergreen_hpd_init()
1852 WREG32(DC_HPD3_CONTROL, tmp); in evergreen_hpd_init()
1855 WREG32(DC_HPD4_CONTROL, tmp); in evergreen_hpd_init()
1858 WREG32(DC_HPD5_CONTROL, tmp); in evergreen_hpd_init()
1861 WREG32(DC_HPD6_CONTROL, tmp); in evergreen_hpd_init()
1890 WREG32(DC_HPD1_CONTROL, 0); in evergreen_hpd_fini()
1893 WREG32(DC_HPD2_CONTROL, 0); in evergreen_hpd_fini()
1896 WREG32(DC_HPD3_CONTROL, 0); in evergreen_hpd_fini()
1899 WREG32(DC_HPD4_CONTROL, 0); in evergreen_hpd_fini()
1902 WREG32(DC_HPD5_CONTROL, 0); in evergreen_hpd_fini()
1905 WREG32(DC_HPD6_CONTROL, 0); in evergreen_hpd_fini()
1961 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1964 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
2385 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2386 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2393 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2394 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2398 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); in evergreen_program_watermarks()
2401 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in evergreen_program_watermarks()
2402 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in evergreen_program_watermarks()
2476 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in evergreen_pcie_gart_tlb_flush()
2478 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); in evergreen_pcie_gart_tlb_flush()
2507 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2510 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2511 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2518 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2519 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2520 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2522 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2523 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2524 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2529 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2531 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2532 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2533 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2534 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2535 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2536 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2537 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2538 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2540 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in evergreen_pcie_gart_enable()
2542 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2557 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2558 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2561 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2563 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2564 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2567 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2568 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2569 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2570 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2571 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2572 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2573 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_disable()
2590 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
2593 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
2594 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
2600 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2601 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2602 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2603 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2604 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2605 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2606 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_agp_enable()
2607 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
2608 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
2732 WREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2748 WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); in evergreen_blank_dp_output()
2763 WREG32(VGA_RENDER_CONTROL, 0); in evergreen_mc_stop()
2774 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2776 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2777 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2783 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2785 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2786 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2808 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2811 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2812 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2825 WREG32(BIF_FB_EN, 0); in evergreen_mc_stop()
2828 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in evergreen_mc_stop()
2839 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2844 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_stop()
2857 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2859 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2861 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2863 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2868 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2869 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2879 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2884 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2889 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_resume()
2903 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); in evergreen_mc_resume()
2905 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in evergreen_mc_resume()
2912 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2913 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2914 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2918 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2919 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2920 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2933 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); in evergreen_mc_resume()
2935 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); in evergreen_mc_resume()
2947 WREG32((0x2c14 + j), 0x00000000); in evergreen_mc_program()
2948 WREG32((0x2c18 + j), 0x00000000); in evergreen_mc_program()
2949 WREG32((0x2c1c + j), 0x00000000); in evergreen_mc_program()
2950 WREG32((0x2c20 + j), 0x00000000); in evergreen_mc_program()
2951 WREG32((0x2c24 + j), 0x00000000); in evergreen_mc_program()
2953 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in evergreen_mc_program()
2960 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in evergreen_mc_program()
2965 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2967 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2971 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2973 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2977 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2979 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2982 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2990 WREG32(MC_FUS_VM_FB_OFFSET, tmp); in evergreen_mc_program()
2994 WREG32(MC_VM_FB_LOCATION, tmp); in evergreen_mc_program()
2995 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2996 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in evergreen_mc_program()
2997 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in evergreen_mc_program()
2999 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
3000 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
3001 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
3003 WREG32(MC_VM_AGP_BASE, 0); in evergreen_mc_program()
3004 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in evergreen_mc_program()
3005 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in evergreen_mc_program()
3063 WREG32(CP_RB_CNTL, in evergreen_cp_load_microcode()
3070 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3072 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
3073 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3076 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
3078 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
3080 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3081 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
3082 WREG32(CP_ME_RAM_RADDR, 0); in evergreen_cp_load_microcode()
3107 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3160 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in evergreen_cp_resume()
3168 WREG32(GRBM_SOFT_RESET, 0); in evergreen_cp_resume()
3177 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3178 WREG32(CP_SEM_WAIT_TIMER, 0x0); in evergreen_cp_resume()
3179 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in evergreen_cp_resume()
3182 WREG32(CP_RB_WPTR_DELAY, 0); in evergreen_cp_resume()
3185 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in evergreen_cp_resume()
3186 WREG32(CP_RB_RPTR_WR, 0); in evergreen_cp_resume()
3188 WREG32(CP_RB_WPTR, ring->wptr); in evergreen_cp_resume()
3191 WREG32(CP_RB_RPTR_ADDR, in evergreen_cp_resume()
3193 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3194 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3197 WREG32(SCRATCH_UMSK, 0xff); in evergreen_cp_resume()
3200 WREG32(SCRATCH_UMSK, 0); in evergreen_cp_resume()
3204 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3206 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in evergreen_cp_resume()
3207 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); in evergreen_cp_resume()
3476 WREG32((0x2c14 + j), 0x00000000); in evergreen_gpu_init()
3477 WREG32((0x2c18 + j), 0x00000000); in evergreen_gpu_init()
3478 WREG32((0x2c1c + j), 0x00000000); in evergreen_gpu_init()
3479 WREG32((0x2c20 + j), 0x00000000); in evergreen_gpu_init()
3480 WREG32((0x2c24 + j), 0x00000000); in evergreen_gpu_init()
3483 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in evergreen_gpu_init()
3484 WREG32(SRBM_INT_CNTL, 0x1); in evergreen_gpu_init()
3485 WREG32(SRBM_INT_ACK, 0x1); in evergreen_gpu_init()
3554 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3555 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3575 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3576 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3584 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3585 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3587 WREG32(GB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3588 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3589 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3590 WREG32(DMA_TILING_CONFIG, gb_addr_config); in evergreen_gpu_init()
3591 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3592 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3593 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3609 WREG32(GB_BACKEND_MAP, tmp); in evergreen_gpu_init()
3611 WREG32(CGTS_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3612 WREG32(CGTS_TCC_DISABLE, 0); in evergreen_gpu_init()
3613 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3614 WREG32(CGTS_USER_TCC_DISABLE, 0); in evergreen_gpu_init()
3617 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in evergreen_gpu_init()
3620 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); in evergreen_gpu_init()
3622 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | in evergreen_gpu_init()
3629 WREG32(SX_DEBUG_1, sx_debug_1); in evergreen_gpu_init()
3635 WREG32(SMX_DC_CTL0, smx_dc_ctl0); in evergreen_gpu_init()
3638 WREG32(SMX_SAR_CTL0, 0x00010000); in evergreen_gpu_init()
3640 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3644 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3648 WREG32(VGT_NUM_INSTANCES, 1); in evergreen_gpu_init()
3649 WREG32(SPI_CONFIG_CNTL, 0); in evergreen_gpu_init()
3650 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in evergreen_gpu_init()
3651 WREG32(CP_PERFMON_CNTL, 0); in evergreen_gpu_init()
3653 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3719 WREG32(SQ_CONFIG, sq_config); in evergreen_gpu_init()
3720 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in evergreen_gpu_init()
3721 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in evergreen_gpu_init()
3722 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); in evergreen_gpu_init()
3723 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in evergreen_gpu_init()
3724 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); in evergreen_gpu_init()
3725 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in evergreen_gpu_init()
3726 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in evergreen_gpu_init()
3727 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); in evergreen_gpu_init()
3728 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); in evergreen_gpu_init()
3729 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); in evergreen_gpu_init()
3731 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in evergreen_gpu_init()
3747 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); in evergreen_gpu_init()
3749 WREG32(VGT_GS_VERTEX_REUSE, 16); in evergreen_gpu_init()
3750 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); in evergreen_gpu_init()
3751 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in evergreen_gpu_init()
3753 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in evergreen_gpu_init()
3754 WREG32(VGT_OUT_DEALLOC_CNTL, 16); in evergreen_gpu_init()
3756 WREG32(CB_PERF_CTR0_SEL_0, 0); in evergreen_gpu_init()
3757 WREG32(CB_PERF_CTR0_SEL_1, 0); in evergreen_gpu_init()
3758 WREG32(CB_PERF_CTR1_SEL_0, 0); in evergreen_gpu_init()
3759 WREG32(CB_PERF_CTR1_SEL_1, 0); in evergreen_gpu_init()
3760 WREG32(CB_PERF_CTR2_SEL_0, 0); in evergreen_gpu_init()
3761 WREG32(CB_PERF_CTR2_SEL_1, 0); in evergreen_gpu_init()
3762 WREG32(CB_PERF_CTR3_SEL_0, 0); in evergreen_gpu_init()
3763 WREG32(CB_PERF_CTR3_SEL_1, 0); in evergreen_gpu_init()
3766 WREG32(CB_COLOR0_BASE, 0); in evergreen_gpu_init()
3767 WREG32(CB_COLOR1_BASE, 0); in evergreen_gpu_init()
3768 WREG32(CB_COLOR2_BASE, 0); in evergreen_gpu_init()
3769 WREG32(CB_COLOR3_BASE, 0); in evergreen_gpu_init()
3770 WREG32(CB_COLOR4_BASE, 0); in evergreen_gpu_init()
3771 WREG32(CB_COLOR5_BASE, 0); in evergreen_gpu_init()
3772 WREG32(CB_COLOR6_BASE, 0); in evergreen_gpu_init()
3773 WREG32(CB_COLOR7_BASE, 0); in evergreen_gpu_init()
3774 WREG32(CB_COLOR8_BASE, 0); in evergreen_gpu_init()
3775 WREG32(CB_COLOR9_BASE, 0); in evergreen_gpu_init()
3776 WREG32(CB_COLOR10_BASE, 0); in evergreen_gpu_init()
3777 WREG32(CB_COLOR11_BASE, 0); in evergreen_gpu_init()
3781 WREG32(i, 0); in evergreen_gpu_init()
3783 WREG32(i, 0); in evergreen_gpu_init()
3787 WREG32(HDP_MISC_CNTL, tmp); in evergreen_gpu_init()
3790 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in evergreen_gpu_init()
3792 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in evergreen_gpu_init()
3997 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4003 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4064 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4070 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4078 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4084 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4107 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
4112 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
4461 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
4474 WREG32(RLC_HB_CNTL, 0); in evergreen_rlc_resume()
4485 WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap); in evergreen_rlc_resume()
4486 WREG32(TN_RLC_LB_PARAMS, 0x00601004); in evergreen_rlc_resume()
4487 WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff); in evergreen_rlc_resume()
4488 WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000); in evergreen_rlc_resume()
4489 WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000); in evergreen_rlc_resume()
4492 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4493 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4495 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4496 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4498 WREG32(RLC_HB_BASE, 0); in evergreen_rlc_resume()
4499 WREG32(RLC_HB_RPTR, 0); in evergreen_rlc_resume()
4500 WREG32(RLC_HB_WPTR, 0); in evergreen_rlc_resume()
4501 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4502 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4504 WREG32(RLC_MC_CNTL, 0); in evergreen_rlc_resume()
4505 WREG32(RLC_UCODE_CNTL, 0); in evergreen_rlc_resume()
4510 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4511 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4515 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4516 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4520 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4521 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4524 WREG32(RLC_UCODE_ADDR, 0); in evergreen_rlc_resume()
4551 WREG32(CAYMAN_DMA1_CNTL, tmp); in evergreen_disable_interrupt_state()
4553 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4555 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4556 WREG32(GRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4557 WREG32(SRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4558 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4559 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4561 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4562 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4565 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4566 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4569 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4570 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4572 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4573 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4576 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4577 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4582 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4583 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4586 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4588 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4590 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4592 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4594 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4596 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4769 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
4771 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
4774 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); in evergreen_irq_set()
4776 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in evergreen_irq_set()
4778 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in evergreen_irq_set()
4779 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in evergreen_irq_set()
4781 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in evergreen_irq_set()
4782 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in evergreen_irq_set()
4785 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in evergreen_irq_set()
4786 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in evergreen_irq_set()
4789 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_irq_set()
4791 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_irq_set()
4794 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_irq_set()
4796 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_irq_set()
4800 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_irq_set()
4802 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in evergreen_irq_set()
4806 WREG32(DC_HPD1_INT_CONTROL, hpd1); in evergreen_irq_set()
4807 WREG32(DC_HPD2_INT_CONTROL, hpd2); in evergreen_irq_set()
4808 WREG32(DC_HPD3_INT_CONTROL, hpd3); in evergreen_irq_set()
4809 WREG32(DC_HPD4_INT_CONTROL, hpd4); in evergreen_irq_set()
4810 WREG32(DC_HPD5_INT_CONTROL, hpd5); in evergreen_irq_set()
4811 WREG32(DC_HPD6_INT_CONTROL, hpd6); in evergreen_irq_set()
4813 WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); in evergreen_irq_set()
4815 WREG32(CG_THERMAL_INT, thermal_int); in evergreen_irq_set()
4817 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); in evergreen_irq_set()
4818 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); in evergreen_irq_set()
4819 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); in evergreen_irq_set()
4820 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); in evergreen_irq_set()
4821 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); in evergreen_irq_set()
4822 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); in evergreen_irq_set()
4859 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4861 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4863 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4865 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4867 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4869 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4873 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4875 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4877 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4879 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4881 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4883 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4888 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4890 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4892 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4894 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4896 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4898 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4904 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4909 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4914 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4919 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4924 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4929 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4935 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4940 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4945 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4950 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4955 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4960 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4966 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4971 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4976 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4981 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4986 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4991 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
5030 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()
5422 WREG32(SRBM_INT_ACK, 0x1); in evergreen_irq_process()
5497 WREG32(IH_RB_RPTR, rptr); in evergreen_irq_process()