Lines Matching refs:offset
170 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, in dce3_2_hdmi_update_acr() argument
176 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset, in dce3_2_hdmi_update_acr()
180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr()
187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr()
190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr()
194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
202 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset) in dce3_2_set_audio_packet() argument
207 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, in dce3_2_set_audio_packet()
211 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, in dce3_2_set_audio_packet()
215 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in dce3_2_set_audio_packet()
219 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in dce3_2_set_audio_packet()
223 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) in dce3_2_set_mute() argument
229 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in dce3_2_set_mute()
231 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); in dce3_2_set_mute()