62 				WREG32(CG_BIF_REQ_AND_RSP, bif);  in cypress_enable_bif_dynamic_pcie_gen2()
126 			WREG32(GRBM_GFX_INDEX, 0xC0000000);  in cypress_gfx_clock_gating_enable()
153 			WREG32(GRBM_GFX_INDEX, 0xC0000000);  in cypress_gfx_clock_gating_enable()
187 		WREG32(GRBM_GFX_INDEX, 0xC0000000);  in cypress_mg_clock_gating_enable()
195 			WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);  in cypress_mg_clock_gating_enable()
208 		WREG32(GRBM_GFX_INDEX, 0xC0000000);  in cypress_mg_clock_gating_enable()
216 			WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);  in cypress_mg_clock_gating_enable()
944 	WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);  in cypress_program_memory_timing_parameters()
1132 		WREG32(MC_CONFIG_MCD, 0xf);  in cypress_force_mc_use_s1()
1133 		WREG32(MC_CG_CONFIG_MCD, 0xf);  in cypress_force_mc_use_s1()
1135 		WREG32(MC_CONFIG, 0xf);  in cypress_force_mc_use_s1()
1136 		WREG32(MC_CG_CONFIG, 0xf);  in cypress_force_mc_use_s1()
1142 	WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);  in cypress_force_mc_use_s1()
1150 	WREG32(MC_SEQ_CG, mc_seq_cg);  in cypress_force_mc_use_s1()
1160 	WREG32(MC_SEQ_CG, mc_seq_cg);  in cypress_force_mc_use_s1()
1173 		WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);  in cypress_copy_ac_timing_from_s1_to_s0()
1190 		WREG32(MC_CONFIG_MCD, 0xf);  in cypress_force_mc_use_s0()
1191 		WREG32(MC_CG_CONFIG_MCD, 0xf);  in cypress_force_mc_use_s0()
1193 		WREG32(MC_CONFIG, 0xf);  in cypress_force_mc_use_s0()
1194 		WREG32(MC_CG_CONFIG, 0xf);  in cypress_force_mc_use_s0()
1200 	WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);  in cypress_force_mc_use_s0()
1208 	WREG32(MC_SEQ_CG, mc_seq_cg);  in cypress_force_mc_use_s0()
1218 	WREG32(MC_SEQ_CG, mc_seq_cg);  in cypress_force_mc_use_s0()
1739 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);  in cypress_enable_display_gap()
1758 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);  in cypress_program_display_gap()
1777 		WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);  in cypress_program_display_gap()