121 	WREG32(reg, (ring->wptr << 2) & 0x3fffc);  in cik_sdma_set_wptr()
266 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);  in cik_sdma_gfx_stop()
267 		WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);  in cik_sdma_gfx_stop()
277 	WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);  in cik_sdma_gfx_stop()
280 	WREG32(SRBM_SOFT_RESET, 0);  in cik_sdma_gfx_stop()
319 		WREG32(SDMA0_CNTL + reg_offset, value);  in cik_sdma_ctx_switch_enable()
351 		WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);  in cik_sdma_enable()
384 		WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);  in cik_sdma_gfx_resume()
385 		WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);  in cik_sdma_gfx_resume()
393 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);  in cik_sdma_gfx_resume()
396 		WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);  in cik_sdma_gfx_resume()
397 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);  in cik_sdma_gfx_resume()
400 		WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,  in cik_sdma_gfx_resume()
402 		WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,  in cik_sdma_gfx_resume()
408 		WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
409 		WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
412 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);  in cik_sdma_gfx_resume()
415 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);  in cik_sdma_gfx_resume()
422 		WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);  in cik_sdma_gfx_resume()
484 		WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()
486 			WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
487 		WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);  in cik_sdma_load_microcode()
493 		WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()
495 			WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
496 		WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);  in cik_sdma_load_microcode()
502 		WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()
504 			WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
505 		WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);  in cik_sdma_load_microcode()
509 		WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()
511 			WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
512 		WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);  in cik_sdma_load_microcode()
515 	WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()
516 	WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);  in cik_sdma_load_microcode()