4161 		} else if (rdev->wb.enabled) {  in cik_ring_ib_execute()
4479 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in cik_cp_gfx_resume()
4497 	WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);  in cik_cp_gfx_resume()
4498 	WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in cik_cp_gfx_resume()
4503 	if (!rdev->wb.enabled)  in cik_cp_gfx_resume()
4533 	if (rdev->wb.enabled)  in cik_gfx_get_rptr()
4534 		rptr = rdev->wb.wb[ring->rptr_offs/4];  in cik_gfx_get_rptr()
4563 	if (rdev->wb.enabled) {  in cik_compute_get_rptr()
4564 		rptr = rdev->wb.wb[ring->rptr_offs/4];  in cik_compute_get_rptr()
4581 	if (rdev->wb.enabled) {  in cik_compute_get_wptr()
4583 		wptr = rdev->wb.wb[ring->wptr_offs/4];  in cik_compute_get_wptr()
4599 	rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;  in cik_compute_set_wptr()
5090 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;  in cik_cp_compute_resume()
5092 			wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;  in cik_cp_compute_resume()
5101 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;  in cik_cp_compute_resume()
5103 			wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;  in cik_cp_compute_resume()
7420 	if (rdev->wb.enabled)  in cik_irq_init()
7424 	WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);  in cik_irq_init()
7425 	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);  in cik_irq_init()
7861 	if (rdev->wb.enabled)  in cik_get_ih_wptr()
7862 		wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);  in cik_get_ih_wptr()